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DAC3174: IO test pattern in dual bus dual clock mode?

Yashpal Singh
Prodigy 20 points
Part Number: DAC3174

Hi,

We are planning to use DAC3174 with FPGA. As we are planning to develop module, we wanted to know more about IO pattern test in Dual mode, Dual bus as there will be no frame, sync because of dual bus, dual clock mode. Also the timing diagram or any details how to send pattern data is also not available. Please let us know how to use SIP_Sync for this testing. Also Do we need to send same pattern on both the bus at the same time???

  • 0
    TI__Guru* 91947 points

    Yashpai,

    You must use SYNC when using IO_test. The rising edge of SYNC will indicate word 0 that you are sending from the FPGA. SIP_SYNC cannot be used for this testing. Basically, SYNC should go high the same time IO_test data word 0 becomes valid as both will be registered by the next rising edge of DA_CLK and DB_CLK. Since there is only 8 registers for the 8 IO_test words, I am guessing the values need to be the same for both buses.

    Regards,

    Jim