hi sir
could you share the ADC3643IRSBT source code for me,
I can't bulid the comm between ADC3643IRSBT & FPGA
Clock need any 1v apply to ADC3643IRSBT?
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hi sir
could you share the ADC3643IRSBT source code for me,
I can't bulid the comm between ADC3643IRSBT & FPGA
Clock need any 1v apply to ADC3643IRSBT?
Hi Alex,
You can download the TSW1400 firmware source code at this link under "firmware": https://www.ti.com/tool/TSW1400EVM
The clock input for the ADC3643 has a Vcm of 0.9 V.
Regards, Amy
Hi Alex,
The firmware TI has available is at the link above (https://www.ti.com/tool/TSW1400EVM). The TSW1400 uses the Altera Stratix IV FGPA and supports both LVDS and CMOS interfaces. The ADC3643 comes with a CMOS to LVDS interposer card that connects to the TSW1400 to support the CMOS DDR mode.
Regards, Amy
Hi Alex,
If you install the ADC35XX GUI you can configure the part in the way you describe. If you would like these writes in a configuration file, you can then create this using the writes found in the GUI.
Regards, Amy
Hi Alex,
I will work on creating a configuration file for you to use. I will get back to you soon.
Regards, Amy
Hi Alex,
Here is the file with the register writes to configurate the part in DDR / 14bit / 65MSPS. You can download it from this link:
https://tidrive.ext.ti.com/a/FlSyX_nUslcEVLJa/43380c2f-15bc-4a25-9bbc-65e34bb55bf0?l
Regards, Amy