I would like you to confirm about power sequence for this device.
Q1. According to datasheet P64, you described power up sequence for this device.
Then, I would like you to confirm about following sentence and Figure 10-1. Initialization of serial registers after power up
* Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
Q1-1. I understand that there are some options for VREF and REFBUF setting.
Which situation does figure 10-1 show ? (It seems that this shows only case of using internal 1.2V (No external supply for REFBUF and VREF))
If "2ms" have not only settling timing byut also meaning of timing when this device latch device status,when should user supply external REFBUF ?
If this device change status dynamically. I can understand meaning of this figure for REFBUF
Q1-2. If user supply both REFBUF and VREF externally, is there any timing restriction b/w ramp up timing of REFBUF and ramp up timing of VREF ?
(According to figure 10-1, you described "ext VREF" but I'm not sure user can supply external REFBUF and VREF at the same time because VREF conditio depends on REFBUF voltage level.)
Q1-3. If user supply both REFBUF and VREF externally, is there any timing restriction b/w ramp up timing of reference(VREF,REFBUF) and ramp up timing of CLK ?
Q2. According to datasheet, it seems there is no description about power down sequence.
Is my understanding that there is no requirement for power down sequence correct ?