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ADC3643: minimum clock amplitude for sampling clock

Part Number: ADC3643


I would like you to confirm about below.

* According to datasheet, maximum and typical "Vid" value is defined.
However, there is no spec for minimum value.

On the other hand, there is following figure in datasheet.

* Figure 6-13. AC Performance vs Clock Amplitude 

According to this figure, TI estimate approximate 0.25V as minimum value of sampling clock.
I think that the reason TI defined only from 1V is stable and best perfomance of SNR become over Vpp = 1V.
In other words, I believe although the noise characteristics are somewhat worse, a minimum of 0.25 Vpp is acceptable as an input.

Is my understanding correct ?
(In case of general LVDS, center value of Vpp is defined 0.7Vpp, so if my above understanding is correct, user can choose such interface.)


  • Hi Ryuuichi,

    Your observations are correct. Figure 6-13 shows the improvement in SNR and SFDR performance as the clock amplitude approaches 1Vpp. This is the typical value provided in the datasheet for this part to work at it's optimal performance.

    Regards, Amy