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ADS1220: Problem using DRDY on Power Up to detect A2D is operational

Part Number: ADS1220
Other Parts Discussed in Thread: TPS22810,

This is a continuation of a previous ticket I submitted (CS0822302). Bob Benjamin has been assisting me. The ADS1220 is powered off, and then power is applied with a Controlled Rise Time Switch (TPS22810). This means the uC is powered during this period. The CS and other SPI (clk, data in, data out) are not initialized until power is applied to the ADS1220. On the CS pin (which is now a GPIO Input), I have enabled the internal pull up on the micro to de-assert the CS with the intent to shield the ADS1220 from inadvertent activity on the SPI (noise, etc). Therefore, while the power is being applied to the ADS1220 (with controlled rise time), the CS voltage follows the ADS1220 power limited by the body diode. There for, the CS voltage is ~0.7 volts higher than the power input and current limited by the internal pullup (47K?). Is this in violation, and will it cause problems?

We then initialize the SPI and send a RESET command to the ADS1220. After 100ms, we check that the DRDY is asserted (Logic Low). On many of our units, this test fails.

Considering all the dynamics here:

- Uc is powered first

- ADS1220 is powered with controlled rise time switch

- SPI is now initialized

- RESET command is sent over SPI to ADS1220

Is there an error in our Power Up sequence?

  • Paul,

    1. I set up hardware and initiated a RESET command. After the reset command is initiated a single shot conversion will execute.  I confirmed that DRDY will go high after the command for 50ms then will drop low indicating that the single shot conversion is complete.  I know this is the behavior you are expecting as well.  I just wanted to let you know that I confirmed this expected operation.
    2. To get continuous conversions, you will need to program your registers and issue a start/sync command. Your test should work to confirm that a single conversion occurs after the reset command.
    3. After the power is fully up, what is the delay before you send the reset command. You will need to wait at least 50us for the power up reset to complete.
    4. It is not clear to me what you mean by the CS being 0.7V higher than the power input. Is power applied to CS before the ramp on the ADC power pins?  If so, the ESD diode on the ADC will allow a parasitic path to the ADC supply.  This could potentially create problems.  Also, in the final setup, is the maximum logic voltage applied to CS and other SPI pins equal to DVDD?
    5. Can you capture the communications signals on a logic analyzer or scope? The scope is useful to check for data integrity issues (e.g. glitches, large overshoot, or other distortion in digital signals).  A logic analyzer is covenant to look at all the digital signals together.  I want to make sure that you are sending the command correctly and also that the digital signal doesn’t have data integrity issues.   The fact that you get intermittent behavior makes me think this may be the issue.
    6. Where did you get the ADS1220 parts? The reason I ask is with the part availability shortage was sometimes see counterfeit devices.

    I hope these questions help us quickly identify your issue.  Thanks for your patience in getting your circuit up and running.


  • Paul,

    In addition to the tests above.  It would be useful if you checked the CS input and supplies with a scope.  I really want to understand if the digital signal is applied before the power.


  • Hi Art,

    We considered using a pull-up to CS before the SPI bus was initialized. However, the only pull-up available is from the uC and is to a 3.3V always on signal. This (as you suggest) could create a back feed to the ADS1220, so we abandoned this approach.