DAC3162EVM: Timing with Internal Clocking

Mark Philip Felipe

Part Number: DAC3162EVM
Other Parts Discussed in Thread: DAC3162

Hi Team, seeking for assistance.

I tried to drive the DAC3162 with an FPGA @ 200MHz. The DAC input is switched from 0x000 to 0xFFF and vice versa at every clock edge to check the full resolution.
I tried to generate the DAC data (DDR format ) as shown in the figure Data transmission format and I send a clock signal 200MHz, Vrms = 0.56V
In attached the input clk and the measured outputs signals (you can check also the simulation signals sended to FMC connector of my FPGA)

I need any suggestion to adjust the timing with internal clocking. As infomation, dac is controlled over a fpga. In attached the received clk from DAC3162 and also the two output signals of the dac.

/resized-image/__size/640x480/__key/communityserver-discussions-components-files/73/InputCLK_5F00_J9.jpg

/resized-image/__size/640x480/__key/communityserver-discussions-components-files/73/waveform-_2800_1_2900_.png

Thank you.

-Mark

over 3 years ago

0 Miguel Lomeli over 3 years ago

TI__Intellectual 1950 points

Hi Mark,

Just to make sure i understand, your trying to delay the clock to meet setup and hold time for proper sampling using your FPGA which is connected to DACEVM?

0 Mark Philip Felipe over 3 years ago in reply to Miguel Lomeli

TI__Genius 10810 points

Hi Miguel,

They tried to output my signals (DDR format as described in data transmission format fig.) but they still get as output signal not as expected

0 Miguel Lomeli over 3 years ago in reply to Mark Philip Felipe

TI__Intellectual 1950 points

Hi Mark,

Can you give me more details on the type of FPGA they are using along with the signals they are testing?

0 Mark Philip Felipe over 3 years ago in reply to Miguel Lomeli

TI__Genius 10810 points

Hi Miguel,

Used in the experiments Zedboard FPGA and tried to drive the DAC3162 with an FPGA @ 200MHz. The DAC input is switched from 0x000 to 0xFFF and vice versa at every clock edge to check the full resolution. In attached the design used to generate the DAC signals (Fig1). In figure the simulation results used the attached design,. Fig 3 shows the measured results.

Fig 1: /resized-image/__size/1000x480/__key/communityserver-discussions-components-files/73/0753.Fig1.PNG

Fig 3: /resized-image/__size/640x480/__key/communityserver-discussions-components-files/73/5280.Fig3.jpg