Other Parts Discussed in Thread: AMC1336
Hi TI team,
I would like to use the AMC1336 in conjunction with the digital CIC3 filters of infineon aurix TC3xx uC's
As I'm designing a function like this for the 1st time, I got some questions
Thanks in advance for the effort and answers
best regards
Stephan Jagusch
1.General Experience / Best Practice / Known Issues
The Infineon Aurix TC3xx Microcontroller Family, has the Function of bypassing the internal DSADC modulators and instead
putting out the clock and return the datastream digitally. Then the datastream can be fed directly into the CIC3 filter chain of the Aurix
--> Is there Experience / known constraints for usage of the AMC1336 in conjunction with the digital part of ifx TC3xx uC DSADC's?
2. CLK output buffer:
The Aurix can output the DS-modulator Clock using to different kind of output ports with different output impedance
FAST buffer : : Z_out [min ; nom , max] = [31, 55 , 80]Ohm
SLOW buffer : Z_out [min ; nom , max] = [125, 225, 320]Ohm
- Can TI make a (reasoned) recommendation, what kind of ports to use and why?
- CLKIN: RC Filters. I found the recommendation of 50Ohm / 10pF RC's within the E2E. Is this still valid for the output buffer decision above?
3. DOUT RC Filters :
What is the output impedance of the AMC1336 DOUT pin ? (I could'nt find it in the datasheet).
4.Signal Delay CLKIN -> DOUT.
For the uC digital Filter chain, it will be important, that the clock is in synch with the datastream. Therefore I need to calculate the "round trip delay". Where the AMC1336 delay contributes
--> What is the "delay" of the AMC1336 (CLKIN -> DOUT). I could'nt interprete
5 Round Trip Latency Compensation:
I thought about an alternative DSADC scenario, where the 20MHz clock is generated by a timer, and the Clock is returned at the AMC1336 side along with the DOUT signal for DSADC reception. This would compensate a lot of the "round trip delay" and would work in advance for the Datastream being "in sync" with the clock
--> Is this scenario known / common? Is it overengineering?
I would be thankful to have the thoughts if TI-engineers of this, as I'm designing this kind of stuff for the 1st time.
6. Layout recommendations CLK / DOUT routing:
I would like to bring the signals over 7..10 cm over the PCB in a quite noisy environment. I never routed that fast single-ended signals and I'm thinking about aspects like
--> Ground planes underneath for shielding (that will introduce parasitic caps)
--> No shielding (susceptability for EMC disturbance)
I would be thankful, if TI could make recommendations for best practice.