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ADC161S626: SPI Data is unstable

Part Number: ADC161S626

Hi expert,

My customer is using ADC161S626.

They give the IN- and IN+ almost the same voltage 2.5V, So the output should be about 0V. 

and they try a twice 16bit read and a three times 8bit read to read the data.

however, they found the data changed too much. 

you can see the waveform below.SPI clock is 5MHz. since the CS is always low. so it will not enter another AD convert,am I right? 

below 2 waveform are all 0V input but the data is totally different.

Does this method not right? however, customer use this method in another project and it works well.

or the SPI clock interval is too long?

The host is IMX6ULL and running linux system. The SPI is configured as below:

BR

Emma

  • Hello Emma,

    The customer needs to use the /CS pin to start each conversion.  Holding /CS low will not work correctly.  The /CS pin can be toggled using a GPIO pin on the host processor, and it should repeat at the desired sample rate.

    The ADC launches data on the falling edge of SCLK; the host processor can read data on the rising edge to meet the setup and hold time requirements. 

    If SCLK is high when /CS transitions low (Figure 41), then the MSB (D15) will launch on the 3rd falling edge of SCLK, and the host processor can read data on the 3rd rising edge of SCLK.  

    Also, if the customer prefers to keep SCLK low when /CS transitions from high to low, then the MSB (D15) will launch on the 2nd falling edge of SCLK, and the host processor can read data on the 3rd rising edge of SCLK.

    Please let me know if the customer is not able to get this working.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Keith,

    The issue is solved, thanks!

    Emma

  • Hi Emma,

    Thanks for the update!  Glad to hear that the customer was able to get everything working.

    Regards,
    Keith