Previously, it has been used with f28377 + CPLD and ads8558 for high-speed acquisition.
For the first revision, the board size was smaller. After re layout, the schematic diagram was deleted, but the periphery of ads8558 remained unchanged, and ads8558 could not realize high-speed acquisition.
For the second revision, f28335 + CPLD is used, the periphery remains unchanged, and ads8558 is normal.
The third revision uses two f28335 + CPLDs, the periphery remains unchanged, and ads8558 cannot realize high-speed acquisition.
May I ask what factors may lead to the failure of ads8558 to achieve high-speed acquisition, and what aspects should we check?
