DAC53508: DAC53508

Hi, and thanks for your answer.

The reason I am using DAC53508 is because of the 8 outputs.

The DAC you are offering is with just 4 outputs.

What is the state that the DAC53508 is reflecting in power off mode?

Do you have a recommendation for a DAC with 8 outputs and with the feature you offered?

Thanks for the support!

Ariel

Hi Ariel,

The DACx3204 would be able to support up to 1.25V of forced voltage when VDD is 0V:

When the DAC53508 is powered off (VDD = 0V) then applying any voltage to the output pins could damage the device. This is typical of most DACs.

When VDD is supplied, the DAC53508 outputs power up in a 10 kΩ to AGND power-down state meaning that the output of your DCDC would start up in an unintended state until you are able to write to the DAC to power the outputs up and set the correct output voltage. If this is ok for your system then there is no issue using the DAC53508

We don't have an 8 channel device with the same features as the DAC53204 at this time.

Best,

Katlynne 

So, to avoid the unintended state in the Power-up, I can use a Pull-down resistor at the output pins, am I right?

in addition, I can use a serial protection resistor (~50ohm) to protect the DAC?

could you please provide me a recommended schematic for DAC53508 in such application of voltage adjustment?

it will be very helpful

thanks!

Ariel

Hi Ariel,

These app notes go over the process:

How to Dynamically Adjust Power Module Output Voltage (see the voltage output DAC section)

Voltage Margining and Scaling Circuit with a Voltage Output Smart DAC

Power-supply margining circuit for SMPS using a precision DAC

Power-supply margining circuit for LDOs using a precision DAC

The last two articles are for the DAC53608 which is the I2C version of the DAC53508. 

By unintended power up, I mean that the DCDC will be brought to a higher voltage when the output of the DAC is 0V. A pulldown would not fix this. If the output were hi-z then the power supply would remain at its nominal output. You can calculate what the output will be when the output is 0V using the below equations from the app note. 

You can see in the LDO article that they are trying to margin the 3.3V nominal supply by ±10% (3.63V and 2.97V). When the DAC output is 0V at startup then the supply goes to about 4V. 

A series protection resistor would limit the current, but the voltage at the output pins should still not violate the maximum ratings of the part which is VDD + 0.3V. The DCDC and DAC would have to power on at the same time to avoid violating this condition. 

Best,

Katlynne Jones