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ADS1259: Question about power rails, reference voltage vs input signal

Adam Porsch
Intellectual 375 points
Part Number: ADS1259
Other Parts Discussed in Thread: ADS127L11, , ADS127L11EVM-PDK, ADS1248, PGA280, REF2025, REF5025, REF5020, REF6025

Hello,

 

I’m working on a project where we have a very mature analog design (15+ years) and we’re trying to design out an older 24-bit delta-sigma ADC that’s no longer available. After looking into all the different parts out there (plus what appears to be well stocked these days…), the ADS1259 seems like a great candidate.

Considering we’re trying to minimize design changes on our mature design, here’s some background info on what’s presently available on our board.

+5V analog power rail, -5V analog power rail, +2.5V reference voltage, -2.5V reference voltage, +5V digital power rail.

Our existing ADC is presently being supplied with a bipolar analog input signal nominally ranging from -2.5V up to +2.5V.

The ADS1259 datasheet indicates it can operate in unipolar mode (AVDD = +5V, AVSS = 0) or bipolar mode (AVDD = +2.5, AVSS = -2.5V). Considering we’d prefer to not add two more power rails to our existing design, we’re leaning towards taking advantage of our existing +5V supply and level shifting up our present +/-2.5V analog input signal to 0V to +5V. To do this we’d implement a new summing amplifier with our stable +2.5V reference already on the board. In addition, it appears we’d need to place a new +5V reference on our board to feed to the ADS1259 Vref+ input, and tie its Vref- to ground, giving us the 5Vref span we need. 

Also keep in mind, as a rough, general rule, we typically try to design a circuit topology around a chip based on the conditions outlined in the datasheet, under the assumption that those conditions provide the best performance and were likely the conditions used for verification/validation of the chip.

That being said, I see in the datasheet, the conditions for the ‘electrical characteristics’ are AVDD = +2.5, AVSS = -2.5, and Vref = 2.5V. Bi=polar mode, but only a 2.5V analog input signal span.

A few things jump out at me:

These performance specs are based on an analog input signal with a span of 2.5V. We’re trying to provide an analog input signal span of 5V.

These performance specs show the chip operating in bipolar mode, whereas we’re looking to operate in unipolar mode. 

The primary question is, are we risking running into some kind of performance/operational pitfalls with the ADS1259, going forward with our proposed topology above, seeing that it deviates from the ‘ideal’ conditions called out in the datasheet? 

I guess I’m a bit confused looking at the 1259 datasheet. All of the ‘ideal condition’ specs are based on a 2.5V ref span, which is only above one-half the available full scale analog signal span that could be provided to the 1259 (AVDD-AVSS + 200mV). Is this to accommodate the signal staying well within the rails and providing a nice, linear, monotonic response? Do we risk degrading linearity or monotonic performance operating with a 5V span for power rails and 5V span for Vref?

The ADS1259EVM kit I just purchased, also comes with an external +2.5V ref chip, which lines up with the data sheet conditions.

Based on that observation, it generally concerns me that we’d be operating close to the rails (5V power span, 5V ref span). At a minimum, I assume we’d need to trim down our existing +/- 2.5V analog signal a bit to stay away from the rails.

Thank you for any insights/contexts you can provide. Naturally, if I’m misinterpreting the datasheet, please let me know.

 

  • 0
    TI__Mastermind 43001 points

    Hi Adam,

    As far as the ADC is concerned, operating at +/-2.5V is generally the same thing as operating at a +5V unipolar supply. I would not expect any performance degradation as a result of using a unipolar versus bipolar supply.

    I believe the specifications are given at VREF = 2.5V because that is the voltage of the ADC internal voltage reference. This is common for ADCs that have an integrated VREF. However, one thing to keep in mind is that the reference voltage needs to be ≤ (AVDD - AVSS + 200 mV). If AVDD = 5V and AVSS = 0V, then the maximum differential reference voltage you can apply is 4.8V. So you would need to attenuate the 5V reference voltage you are generating or you will be operating outside of the ADC recommended conditions. You could also operate the ADS1259 at 0V and 5.2V to use a 5V VREF, but I imagine that would be challenging as well.

    Something else to consider: we have just released a new ADC, the ADS127L11. This ADC is effectively a next-generation version of the ADS1259 without the integrated VREF, which you are not using anyway. The ADS127L11 is also smaller and does not have the VREF limitation like the ADS1259. I mention this device mainly because I know you might have some concerns about longevity, especially with a device that is 10+ years old like the ADS1259, so I wanted to present this as an option to you.

    Let me know if you have any additional questions.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 375 points

    Bryan,


    Thank you for the quick response.  

    Regarding the Vref, I apologize, but I'm a bit confused by your response. Based on the MIN, TYP, and MAX columns of the data sheet:

    If I plug in AVDD = 5.0V, AVSS = 0.0V to the equation and follow algebraic order of operations from left to right, I assume I'd get the following:

    Vref (MAX) = 5.0V - 0.0V + 0.2V = 5.2V, therefore I'd assume a Vref span of 5V would be within range?

    Regarding the 127L11, I agree, it's looks like a great chip. In fact, I have the ADS127L11EVM-PDK eval kit in my possession (along with the ADS1259EVM-PDK). In normal times, I'd likely plan to move forward with it, considering its new and has the best chance of 10+ year longevity. However, I haven't seen any stock available on TI.com nor digikey/mouser etc. Not knowing when the chip shortage will end nor knowing the mfg output/rates of one chip vs another, the only thing I have to go on is existing stock, buying several thousand chips (1-2 years worth) and hoping everything gets back to normal soon. If you have any insights on the 127L11 lead times/projected mfg schedules to provide some confidence that steady supply will be available later this year and forward, I'd be very interested.

  • 0 in reply to Adam Porsch
    TI__Mastermind 43001 points

    Hi Adam,

    Indeed you are correct! I read this too fast and assumed it was like some other products that do have a headroom limitation on the VREF input e.g ADS1248.

    Therefore, you should be good to go as far as using a 5V VREF. Thanks for catching that error.

    Let me look into the supply for the ADS127L11. I might have someone else on our team reach out to you about this.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 375 points

    Bryan,

    That's no problem! I'm sure you're juggling many forum posts each day, easy to overlook something like that.

    A follow up question about the 1259 and it's rail/ref config...

    I found another reply of yours (see link below) regarding the 1259 and, assuming AVDD=+5V/AVSS = 0V, one can apply a +2.5V reference signal to AIN-. This then allows AIN+ to swing from 0V to +5V. The result of his topology is we can take advantage of all the resultant 2’s compliment codes using a +5V unipolar supply to the 1259. Please note, your technique specifically states to put the 1259 into internal REF mode and feed the REFOUT into AIN- (as opposed to using an external reference and feeding that to both REFP and AIN-). 

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/995585/ads1259-ads1259/3677601?tisearch=e2e-sitesearch&keymatch=ADS1259%252520reference#3677601

    I have the ADS1259EVM-PDK. I wanted to try out your suggested technique. Using ADC pro and the correct jumper settings, I fed REFOUT into AIN-. I then used a Lake Shore Cryotronics Precision 155 Source and hooked its positive Vout to AIN+ (TP7) and it’s return to GND (TP6). Using ADC pro, I was able to configure the ADS1259 for ‘internal ref mode’, capture some ADC data, and get the +2.5V down to -2.5V codes I expected. I should note, I have S2 set to HDR so the PGA280 outputs are divorced from the inputs to the 1259.


    The next step was for me to try this technique using the external reference on the EVM board (U11- REF5025ID). I set the ADS1259 EVM board up accordingly by moving the S1 switch to the right (thus selecting the REF5025ID). I then took the REF2025 +2.5V output available on the REFP test point, and jumpered it to AIN- (TP8). I still have my 155 0->+5V source hooked up as before to AIN+ (TP7) and ground (TP6). 

    When I set my 155 to +2.5V, the resultant differential input V to the 1259 (AINP – AINN) is about 0, just as I expect. However I then bumped the 155 up to +5V out (just like the previous test) and the differential voltage was not +2.5V, but a couple 100mV lower. To investigate, I then measured my AIN- to GND with a meter, and observed it was 160mV above my expected +2.5V, sitting around +2.630V!

     

    I then took the test to the other direction and brought the 155 output to 0V, thus creating a nominal -2.5V input (AINP – AINN) to the 1259. To my surprise, the ADC reported differential voltage was lower again. This time, when I measured AIN- to GND, instead of the expected +2.5V, I was seeing +2.34V, about 160mV lower than the expected +2.5V.

     

    In summary, using the 5025 +2.5V ref and feeding it to the REFPos/AIN- pins, that voltage increases as AINP increases above +2.5V, and it decreases as AINP goes below +2.5V. Do you know what might explain this phenomenon?


    Thinking that I might be overdriving the REF5025, I took a second 155 voltage source to provide a stronger 2.5V bias to the AIN- pin. Lo and behold, I got the expected behavior as the case you suggested of bringing out REFOUT to AIN-. On the surface, it would appear I might be asking the REF5025 to source too much current by feeding to both REFIN+ and AIN-, but considering the 10kOhm series resistor plus 100’s ofkOhm imput impedance on the 1259, the ref should only be sourcing 100’s of uA.

    I can’t wrap my head around the observed increase/decrease in the +2.5V REFP/AIN- voltage as a function of the voltage provided on AINP.

    I appreciate you looking into this, as I’d really like to consider this ‘2.5V bias toplogy’. It would integrate nicely into our existing design, since we already have +5V supply and a +2.5V ultra stable reference on the board.

  • 0 in reply to Adam Porsch
    TI__Mastermind 43001 points

    Hi Adam,

    Can you try reducing the 10k resistor at the output of the REF5025 and see if that makes a difference? You could probably just make this 0 ohm just for this test.

    -Bryan

  • 0
    TI__Prodigy 71 points

    Hi Adam,

    ADS127L11IPWR is our new & popular product. We can currently support 1000s Qty with much shorter lead time( 6 to 7 weeks).

    Regards,

    Sheetal

  • 0 in reply to Bryan Lizon86
    Intellectual 375 points

    Bryan,

    Great suggestion!


    I removed the 10k resistor on the output of the REF5025 and now our AIN- biased at +2.5V topology works fine, with the REF5025 driving both the AIN- pin and the REFIN+ pin.

    I see now that there's ~130kOhm of resistance on VIN (AINP-AINV). Even with a worse case ~17uA of current required by the AIN- pin (with Vin @ 2.5V), it turns out there was enough of a voltage drop on the REF5020 external 10kOhm resistor to increase/decrease my Vref+/Ain- +2.5V by 100-200mV in either direction (depending on the polarity and magnitude of VIN).

    So, in conclusion, would the following circuit config be considered normal operating conditions of the ADS1259 and therefore meet the specs as called out in the datasheet?

    AVDD = 5.0V

    AVSS = 0.0V (gnd)

    RefInPos = +2.5V (externally supplied)

    RefInNeg = 0.0V (gnd)

    AnalogInNeg = fixed +2.5V = tied to RefInPos

    AinPos = 0V -> +5V input range. (our analog circuit likely trimmed inward a couple % from both directions, and clamped, just to prevent VIN to every get right at or over the rails)

  • +1 in reply to Adam Porsch
    TI__Mastermind 43001 points

    Hi Adam,

    This should work in theory. As you can see though, in practice there might be additional factors in the circuit that lead to non-ideal behavior e.g. the resistor between the VREF output and ADC input (not sure why it was so large, maybe because the ADS1259 has an integrated buffer on the VREF input, and the PGA280 is also high impedance, so it didn't really matter). You might consider something like the REF6025, which has an integrated buffer to help isolate the VREF output from the unbuffered ADC input.

    Also, consider that the source impedance can have the same effect on the AINP pin. It therefore might be a good idea to either buffer both ADC inputs using a low-noise, high accuracy dual amplifier (and use the unbuffered REF5025 in this case) or ensure that the source impedance is low (<1kohm).

    Otherwise, I think you are good to go.

    Also please note the comment from my colleague Sheetal about the ADS127L11 availability.

    -Bryan

  • 0 in reply to Sheetal Liddar
    Intellectual 375 points

    Sheetal,

    Thank you for the feedback. I've gotten similar feedback (suggesting 127L11 over 1259) from our regional TI Field Application engineer.

    I'm going to pivot my focus over to the 127L11 eval kit I have.

    Admittedly, I've been a bit skiddish in the last 6-12 months, when looking into new designs, considering a chip that shows zero inventory for weeks on end.

    It's been difficult to know what metrics to trust when it comes to availability and lead times (seeing other chips from other manufacturers that in the past were, say 10 week lead times, suddenly jump to 52 or even 90 weeks!). 

    But, I've been consistently hearing and seeing the 6-7 lead week lead time for this chip, so that helps ease those concerns.

    It seems there's a big push by TI with this chip. Is it safe to say with reasonable confidence that this chip will remain a higher priority for production lines and not fall into the 52 lead week trap?

  • 0 in reply to Adam Porsch
    TI__Prodigy 71 points

    Hi Adam,

    For new device release we typically  have a ramp plan so that we can support initial ramp of any customer end product. I don't anticipate in near term increase lead time for this device but it depends on what order we receive from other customers.

    When do you expect product ramp of your product & what is estimated quantity need?

    Placing orders will be the best way to secure material.

    Regards,

    Sheetal