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ADS7957: Wrong output after ESD

Part Number: ADS7957
Other Parts Discussed in Thread: STRIKE

Hi Team,

My customer found after applied 15kV air discharge and 5kV contact discharge ESD test, the output is FFC, even with input shorted to ground. 

They tried two ways below, both can help the device recover:

1. write 1 to DI09 to soft reset the device, output is back to normal

2. set DI08 to1 and pull high GPIO3 to keep ADC in active mode, the output is always normal even after the ESD even

What do you think the possible issue it is? Is it any possible way to set the device in power down mode during ESD? 

If set DI08 to 1 and pull GPIO3 to high can solve this problem, is there any potential risk for this setup? 

Thanks,

Cera 

  • Hi Cera,

    Is the customer adding any external ESD protection around the device? If so, can you clarify what protection there is? A schematic would also be helpful. I am doubtful the device is rated for this level of ESD so the best way to protect the device would be to add some external protection such as TVS diodes. 

    Regarding DI08, I assume you are referring to the GPIO Configuration register. If that's the case, I don't see an issue with setting it as a Power-down control and pulling it up high. However, I don't believe this to be a solid solution. Best action would be to properly protect the device with external ESD protection. 

    Regards,

    Aaron Estrada

  • Hi Team,

    Before the failure occurs, there is a filter circuit at the front end of each input channel; after the failure occurs, TVS and ESD protection devices are added to the front end of the input channel, but the failure has a certain probability of recurrence. After modifying DI08, the fault did not reproduce.

    Thanks,

  • Hi Yanjie,

    What ESD protection is added and where is it locate? Is there protection only on the analog inputs? Is there a schematic available to provide?


    Regards,
    Aaron Estrada

  • Hi Team,

    The specific measures include connecting an ESD electrostatic protection device in parallel with the input terminal bit number C71 and soldering a TVS diode on the bit number D70. The chip power pin and ground are directly connected to TVS in parallel.

  • Hi Yanjie,

    Is only CH0 tested? From the schematic, I cannot tell if there is ESD protection on all of the channels that are used. Can you clarify where the focus of ESD is? Is it focused at the inputs of the device?

    I don't see an issue with keeping the power-down GPIO pulled high as that is common but again, I don't think it's a concrete solution. If you can provide more details of the ESD testing then that would be great. Ultimately, ESD protection should be added on the device pins where ESD is present. It's possible that the ESD strike is making its way to an unprotected pin and causing this sort of latch up behavior. 


    Regards,
    Aaron