Other Parts Discussed in Thread: ADS41B29,
we tried to use the ADS41B29 to convert the received IF signal to digital data. We connected the ADS41B29EVM to the Xilinx FPGA board using the FMC-ADC adapter.
The ADS41B29 is configured to CMOS interface 2's complement output with the 250MHz input clock. The input signal (IF) frequency varies from 20MHz to 50MHz and different amplitude. The FPGA logic also uses 250MHz to continuously sample the 12bit data.
We found that the data is unstable and noisy time by time. For example, after a high amplitude data, the 10th bit is supposed to be low level, but the bit is kept at high. This problem will also happen in other bits. We have check it by using a oscilloscope.
Please provide some suggestions / advise to resolve it ?