DAC8568: Trying to exchange our AD5668-BRUZ with this DAC

Hi ,

Thanks for considering TI device. 

1. Are you using internal or external reference ?

2. Could you please share register write sequence  to look the issue.

Thanks 

Hi, 

Thank you for the fast response.

We are using an external reference of 5 V for the "AD5668BRUZ-3" and exchanged it with an external reference of 2.5 V for the "DA8568D".

In the following part I have the commands which writing on the register. We are using a DMA and a McBSP.

void Init_DAC_structure(void)
{
  char axis;

  for(axis=0; axis < MAX_AXIS ; axis++)
  {
    DAC_Axis[axis].Sinus.bits.channel = 2*axis;      // Channelnumber of DAC for Sinus of the axis

    DAC_Axis[axis].Sinus.bits.rsvd2 &= ~(1 << 4);	// Set Bit DB32 of the Input Shift Register to 0 (für DAC8568)

    if(axis == 0)
      DAC_Axis[axis].Sinus.bits.command = 2;         // write Input-Register of DAC und update alle Kanaele
    else
      DAC_Axis[axis].Sinus.bits.command = 0;         // write Input-Register of DAC
    DAC_Axis[axis].Cosinus.bits.channel = 2*axis+1;  // Channelnumber of DAC for Cosinus of the axis
    DAC_Axis[axis].Cosinus.bits.rsvd2 &= ~(1 << 4);	//  Set Bit DB32 of the Input Shift Register to 0 (für DAC8568)
    DAC_Axis[axis].Cosinus.bits.command = 0;         // Write Input-Register of DAC
  }
}

void Init_dma_4_mcbspa()
{
  // Channel 1, McBSPA transmit
  EALLOW;
  DmaRegs.DMACTRL.bit.HARDRESET = 1;                                // DMA-Reset
  asm(" NOP");                                                      // 1 Cycle delay needed
  DmaRegs.DMACTRL.bit.PRIORITYRESET = 1;                            // needed for setting DMA-Channel to highest priority
  DmaRegs.PRIORITYCTRL1.bit.CH1PRIORITY = 1;                        // DMA-Kanal 1 (target value output) has the highest priority 
  DmaRegs.CH1.MODE.bit.CHINTE = 0;                                  // Interrupt to CPU through DMA-Kanal 1 disabled
  DmaRegs.CH1.MODE.bit.CHINTMODE = 1;                               // dont care, if  Interrupt to CPU then after transfer of all target values
  DmaRegs.CH1.MODE.bit.DATASIZE = 0;                                // 16-bit-Data-Transfer-Size
  DmaRegs.CH1.MODE.bit.SYNCSEL = 0;                                 // dont care
  DmaRegs.CH1.MODE.bit.SYNCE = 0;         	                        // No Sync-Signal
  DmaRegs.CH1.MODE.bit.CONTINUOUS = 0;                              // DMA is stopped after full data transfer (RUNSTS-Bit = 0)
  DmaRegs.CH1.MODE.bit.ONESHOT = 0;                                 // only 1 burst transfer per Event-Trigger (McBSPA)

  DmaRegs.CH1.MODE.bit.PERINTE = 1;                                 // Interrupt der DMA through Pheripherie (McBSPA) enabled
  DmaRegs.CH1.MODE.bit.OVRINTE = 0;                                 // Overflow Interrupt disabled, should not happen
  DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA;                      // Peripheral-Interrupt-Quelle = McBSP MXSYNCA (14)

  DmaRegs.CH1.BURST_SIZE.all = 1;                                   // x+1 = 2 Words/Burst
  DmaRegs.CH1.SRC_BURST_STEP = -1;                                  // source address post-increment/decrement step size while processing a burst of data
  DmaRegs.CH1.DST_BURST_STEP = 1;                                   // destination address post-increment/decrement step size while processing a burst of data

  DmaRegs.CH1.TRANSFER_SIZE = 7;                                    // x+1 = 8 Bursts/Transfer
  DmaRegs.CH1.SRC_TRANSFER_STEP = -1;                               // Source-Adress after Burst increment by 1
  DmaRegs.CH1.DST_TRANSFER_STEP = -1;                               // Set adress of DXR1 to DXR2 

  DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &DAC_Axis[MAX_AXIS-1].Cosinus.all.HighWord;      // Starting Address = buffer
  DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &DAC_Axis[MAX_AXIS-1].Cosinus.all.HighWord;  // Not needed unless using wrap function

  DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all;		  // Start Addresse = McBSPA DXR
  DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all;  // Not needed unless using wrap function
  DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;                               // Put to maximum - don't want destination wrap
  DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;                               // Put to maximum - don't want source wrap
  DmaRegs.CH1.DST_WRAP_STEP = 0;                                    // not used
  DmaRegs.CH1.SRC_WRAP_STEP = 0;                                    // not used

  DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;                               // Clear Sync-Error-Flag
  DmaRegs.CH1.CONTROL.bit.SYNCCLR =1;                               // Clear Sync-Event-Flag
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;                            // Clear any spurious interrupt flags
  EDIS;
}

void InitMcbspa(void)
{
// McBSP-A register settings

    McbspaRegs.SPCR2.all=0x0000;		// Reset FS generator, sample rate generator & transmitter
	McbspaRegs.SPCR1.all=0x0000;		// Reset Receiver, Right justify word
	McbspaRegs.SPCR1.bit.DLB = 1;       // Enable loopback mode for test. Comment out for normal McBSP transfer mode.


	McbspaRegs.MFFINT.all=0x0;			// Disable all interrupts

    McbspaRegs.RCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Receive)
    McbspaRegs.RCR1.all=0x0;

    McbspaRegs.XCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Transmit)
    McbspaRegs.XCR1.all=0x0;

    McbspaRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
	McbspaRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source

    McbspaRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
	McbspaRegs.SRGR2.bit.FPER = 31;		// FPER = 32 CLKG periods

    //McbspaRegs.SRGR1.bit.FWID = 0;              // Frame Width = 1 CLKG period	//the new DAC needs at least 2 better 3 CLKG periods
	McbspaRegs.SRGR1.bit.FWID = 2;				// Version for DAC8565 Lesezeichen
    McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;	// CLKG frequency = LSPCLK/(CLKGDV+1)

    delay_loop();                // Wait at least 2 SRG clock cycles

    McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
	clkg_delay_loop();           // Wait at least 2 CLKG cycles
	McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
	McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
    McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset

}

Hi Moritz,

Sorry, i unable to understand source code. Could you please share pseudo code sequence of DAC.

The following description describes the DAC code sequence.

Init_DAC_structure:

for every DAC output do:
{
Define the even numbered DAC output channels as Sinus (in the Input Shift Register)

Set Bit32 (DB32) of the Input Shift Register for the even channels to 0 (needed for DAC8568)

if the for loop is on his first loop:
{
	Write the Input Register of the DAC and update all channels
}
else
{
	Write the Input Register of the DAC of the even numbers
}
Define the odd numbered DAC output channels as Cosinus (in the Input Shift Register)
Set Bit32 (DB32) of the Input Shift Register for the odd channels to 0 (needed for DAC8568)
Write the Input Register of the DAC for the odd channels to 0 (needed for DAC8568)
} 

Hope this makes this part a bit more understandable. I did send the other parts aswell because we are using Mcbspa to send the digital data from the "TMS320F28335" Controller to the DAC. 

Hi Mortiz,

To narrow down problem , 1st will try it on single channel instead of updating all 8 channels

1. Try sequence for channel 0 and check how it behaving?

2. share your schematic.

3. share scope snap for SPI singals(SYNC, SCLK and DIN)