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ADC09QJ1300-Q1: rx_sync signal is not always high

Part Number: ADC09QJ1300-Q1

Hi, TI's  experts. 

 had some difficulties with my project.  I am  trying to   connect   ADC09QJ1300-Q1  to  ZYNQ-7000(xc7z100) on my board.   

The   circuit block diagram  is same with 《adc09qj1300-q1.pdf》 Figure 9-1. Typical  Configuration for a LiDAR Digitizer.    Following  is my configuration: 

On  the ADC side,

The adc chip's  reference clock uses  pin  "SE_CLK",  100MHz clk  input.     

JMODE  = 0,   K =4,  JESD‘s  serdes line_rate = 4.8Gbps.

ADC’s  sample rate = 600MSPS.

TRIGOUT±  frequency  is  4.8G / 32 = 150MHz,   as  FPGA‘s  Serdes PHY  ref clock.

SYSREF  = 4.8G / 10*F*K  = 4.8G / 10 * 8 *4  = 15MHz,  pulse signal not periodic  signal,  from  FPGA. 

PLLREF±  = 100MHz ,  output to  FPGA.

On  the FPGA  side: 

PLLREF± comes from adc  is the  main clock source, input  to  FPGA innner MMCM.  From  MMCM ,   I  get  FPGA  jesd's  glbclk , 120MHz (4.8G / 40),

SYSREF  = 4.8G / 10*F*K  = 4.8G / 10 * 8 *4  = 15MHz,   give  it  to   FPGA  and  ADC.                                                      

Here is  my  question:  

Most of  time, FPGA  jesd_rx can  receive  normal data,  and  rx_tvalid,  rx_tdata[255:0] ,   rx_sync  is ok.  But i  can also observe some strange  logic timing.  Look  at   following  pic,


  • Sometimes,rx_sync will  get  low  and  vibrate.  Is  it  normal? Hope to  receive your  advise.  

  • Hi Zeng,

    The SYNCn signal can be used by the Rx to indicate an error condition (and hence re-initialize the link). Please check if you have enabled error reporting via SYNC in the IP. This is part of the CTRL_8B10B_CFG register in the IP. 

    I believe you have a timing closure issue with the SYSREF sampling, because you are using a 100MHz input (PLLREF) to generate 120MHz using the FPGA PLL. However, SYSREF will have guaranteed relationship only to the 100MHz clock, so it will not be sampled correctly on some of the 120MHz edges.



  • Thank your reply and analysis.  Problem has been resolved.  The problem is truly in clock scheme.   Now  i  implement  it  like this:   PLLREF±  goes into MMCM in FPGA,  and  it  generates  120Mhz .  120MHz have 2 roads,  one to FPGA  JESD204 ip core glbclk,  the other to divided to 15Mhz pulse signal  and give it to FPGA,  external  ADC.    Now,  FPGA jesd_rx  interface signal  rx_sync is always high  when initialization is done.