ADC12DJ3200EVM: Need to purchase TI card which has both ADC and DAC devices on it.

Thakur Rohit Singh

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: AFE7900

Hi team

Looking to purchase a module/kit which has both ADC and DAC devices on it with JESD204B/C interface. The goal here is to perform a complete loopback from ADC--> FPGA Rx--> FPGA Tx--> DAC. Basically giving analog input to ADC and getting the same signal as output from DAC. Below are the specific requirements.

1) For the loopback path( ADC--> FPGA Rx--> FPGA Tx--> DAC),we first look to perform PRBS tests for bit errors. Hence, requirement is to have same PRBS patterns both on ADC and DAC side as internal pattern. So complete loopback path can be tested for bit errors.

2) Support JESD204B/C.

Quick responses are really appreciated as we need to take a call on this.

Regards

Rohit

over 3 years ago

0 Rob Reeder over 3 years ago

TI__Mastermind 39050 points

Hi Rohit,

I am working on a suggestion for you.

I will let you know.

Thx,

Rob

0 Rob Reeder over 3 years ago in reply to Rob Reeder

TI__Mastermind 39050 points

https://www.ti.com/product/AFE7900#design-development

Hi Rohit,

I would look into the AFE7900. This has both ADCs and DACs on the same device and supports JESD204B/C.

Thanks,

Rob

0 Thakur Rohit Singh over 3 years ago in reply to Rob Reeder

Prodigy 130 points

Hi Rob Reeder

Thank you very much for the link. I think the full data sheet for AFE7900 is not available. I have requested for it though but not sure when will be it available.

Can you answer me whether this will help me to test full loopback path? Specific question below:

2) Is there any GUI available to program the register bits for ADC and DAC?

Rohit

0 Thakur Rohit Singh over 3 years ago in reply to Thakur Rohit Singh

Prodigy 130 points

Hi Rob Reeder

After going through the full data sheet, here are some more observations.

1) We have PRBS patterns at TX, RX at SERDES (PHY) level. But how to enable this?

2) I didn't see other internal test patterns in the data sheet like ramp, K28.5 etc. Are we not supporting internal patterns.

3) I see there is SPI interface to help configure the ADC,DAC registers. Where can i find the register map.

Regards

Rohit

0 Vijayendra Varma Siddamsetty over 3 years ago in reply to Thakur Rohit Singh

TI__Genius 10865 points

Hi Rohit,

Both PRBS generators in AFE’s SERDES transmit lanes and PRBS checkers in AFE’s SERDES receiver lanes support PRBS9, 15, 23 and 31. So, it is possible to test as you want to: ADC--> FPGA Rx--> FPGA Tx--> DAC.

The register set document is available in secure folder (www.ti.com/mysecuresoftware). You can refer to SBAU337_Register_Set_13th_May_2020.pdf.

The EVM control software installer is also available on secure folder.

JESD ramp mode is supported. Note that this test pattern is before JESD encoding unlike the PRBS pattern from SERDES block. Refer to ‘AFE79XX_Latte_UserGuide.pdf’ for functions to be executed to enable test patterns.

Regards,

Vijay

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ADC12DJ3200EVM: Need to purchase TI card which has both ADC and DAC devices on it.