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ADS1241 - Crystal and Capacitance Guide

Poh Leong Ng
Intellectual 745 points
Other Parts Discussed in Thread: ADS1241

The problem encountered here is that sometime there is no oscillation. Please find the schematic below:

What could have resulted in this? Is there a layout guide on how to place the crystal. My thought is that the crystal should be as close to the XIN and XOUT pins as possible, keeping the traces short. Based on the datasheet, 20pF should meet the requirement. What else do I need to take note?

  • 0
    TI__Guru** 113765 points

    Poh Leong Ng,

    I'm not sure if you are using one of the ADS1241 datasheet recommended crystals, but  not all crystals are constructed or respond the same. 

    You are correct about the trace lengths and crystal placement.  However, even if the traces are short there can be added capacitance in the trace or circuit connections.  We have found that start-up problems may exist because parasitic capacitance can add to 20pF caps already being used.  You might try reducing the value of C1 and C2, or even removing them altogether to achieve better start-up performance.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 745 points

    Hi Bob,

    Thanks for the suggestion. I have gotten the layout of the ADS1241. Please find attached picture.
    It is a 4-layer board, ADS1241 and crystal on first layer, second layer is solid ground.

    0451.Layout.ppt

    I find the layout is a bit messy and could be cleaned up further. My thinking is that the test points should be removed as it could affect the overall capacitance.
    I have searched the Internet and found a good guide on oscillator routing below. As a best practice guide, I assume the document provides a good reference to review and change the layout.

    http://focus.tij.co.jp/jp/lit/an/swca076/swca076.pdf

    I would like to suggest that the layout be something like below: Feel free to comment.

  • 0 in reply to Poh Leong Ng
    TI__Guru** 113765 points

    Poh Leong Ng,

    There is good basic information in the app note you refer to, but remember the circuit is designed slightly different between devices as the frequencies involved are quite different.

    There are a lot of sources for stray capacitance, and some may be from the vias, but are also in the trace lengths and device connections as well.  It takes only very small differences to come up with pFs of capacitance.  So, using the maximum load cap values for a crystal will probably cause the crystal not to start in some cases (maybe never.)  This is true even with optimal layout because the trace is over the ground plane and acts as a capacitor (two conductors with a dielectric between.)

    The layout you propose assumes a through-hole crystal and probably caps larger than 0603 because you have a trace that runs under the cap where there will be some added stray capacitance from the trace to the ground pad. 

    The basic layout concept is really short traces and a symmetric circuit with very low impedance paths to ground (which also includes the ground via connections.)

    Best regards,

    Bob B