ADS1257: ADS1257 Measurement error (gain error)

Hello.

Write additional information.

After the initialization was completed with the same settings, 4.8V was input to AIN0 from the high precision reference power supply, and the SYSGCAL (System gain calibration) command was sent before measurement.

The results are as follows.

REF = 2.4V, AIN0 = 2.4V, AIN1 = 2.4V → OUTPUT 0xFFFF91 (-0.00032V)

REF = 2.4V, AIN0 = 4.4V, AIN1 = 2.4V → OUTPUT 0x6AAAC9 (2.000009V)

REF = 2.4V, AIN0 = 4.8V, AIN1 = 2.4V → OUTPUT 0x7FFFFF (2.400001V)

When System gain calibration is performed, the output shows the ideal value for the input.

The circuit configuration has not been changed, but if SELFGCAL (Gain self-calibration) is executed, the operation will be the same as the one that was surrendered earlier.

I feel that SELFGCAL (Gain self-calibration) is not working properly. Is it possible to improve the procedure?

Or is it not possible to measure with high accuracy without performing System gain calibration?

Hi. Brian-san

Thank you for answering.
I will post a test schematic.
For the circuit configuration of the test circuit, refer to "Fig. 60. Basic connection of ADS1257" in the data sheet.
We also measured the voltage at each point, so check it.

TEST_ADS1257(PDF).pdf

When the voltage of the input pin (AIN0, AIN1) of AD was directly measured, the input voltage fluctuated at the sampling timing.
Also, as a result of measuring the voltage across the filter circuits R7 and R14 with an oscilloscope, it seems that a large current is flowing in the AD converter at the sampling timing.

The test circuit is almost the same as the basic connection circuit of the data sheet except for the input buffer (OP284).
It is thought that the same phenomenon occurs when measuring with the circuit of "Fig. 60 ADS1257 Basic connection".

Is there a problem with the circuit configuration?
Is it possible to improve by changing the circuit configuration or SPI programming?
If you have any advice, please let me know.

(I am using translation software. I'm sorry if the expression is difficult to understand.)

Hi Umezawa-san,

I am confused as to what the actual issue is here. Are we still talking about a small error that is removed when you perform the SYSGCAL?

The voltages you are showing in the scope shots appear for about 40-60ns, while the actual spike duration is ~10ns. How often does this repeat? You said at the "sampling timing" - is that the modulator frequency or the output data rate (ODR)? If the spike repeats at the ODR, what ODR are you using?

Keep in mind that the modulator sampling frequency is ~ 500 ns when the gain = 2, so this voltage spike would not even be perceptible to the ADC (it basically gets averaged out). The sampling period is shown in the image below.

Also, the translation is good as far as I can tell.

-Bryan

Hi Bryan-san,

I'm sorry for the confusion.
First, the spike in the scope shot seems to be the timing of switching the MUX channel. (My oscilloscope couldn't measure the exact timing.)
As Bryan-san says, I understand that this voltage spike is not recognized by the ADC due to averaging.

What I don't understand is the cause of the error removed by SYSGCAL.
(For me this error is not small and I want to understand the cause.)

I thought the cause was as follows.
(Only SELFCAL is executed. SYSGCAL is not executed.)

When the ADC is used with PGA = 2, the input impedance of the ADC is ZeffA = 130kΩ and ZeffB = 110kΩ.
("Figure 27. Analog Input Effective Impedances with Buffer Off" and "Table 8. Analog Input Impedances with Buffer Off" in the datasheet)

Since the ADC input filter circuit resistors 300Ω are connected in series, the resistance voltage divider causes the voltage to drop at the ADC input pins.
For this reason, we thought that the ADC would show a lower value than the voltage value input from the reference power supply.
(Simulation results are attached.)

ADS1257 Input_Impedances VS 300Ω.pdf

Is this understanding correct?

Hi Umezawa-san,

One action you can take is to enable the ADS1257 buffer to see if the error is eliminated. This will help determine if the issue is related to the ADC input impedance (though having buffered inputs via the OP284 should basically be the same as turning on the ADC input buffer). If you do try this test, make sure that the input voltages are within the ADC range as specified in the datasheet. The absolute input voltage on each pin must be <AVDD - 2V with the buffer enabled. I know your system voltages are beyond this level, but you can just apply test voltages that are <AVDD-2V to see if enabling the ADC buffer makes a difference.

You also have no filter resistors on the VREF inputs. You might try adding a 301-ohm filter resistor to the REFP input and removing capacitor C9. This will make the filtering more similar between the VREF and AINx inputs. I have seen this cause issues at other customers in the past.

Please let me know the outcome of these tests.

-Bryan

Hi Bryan-san,

I got the following comparison data.
1. Comparison data when buffer is enabled / disabled
2. Comparison data when buffer is enabled / disabled when 300Ω is added and C9 is removed.
please confirm.

comparison data.pdf

Data is acquired for VREF and input voltage in consideration of the input voltage range when the buffer is enabled.
There is a difference between the data when the buffer is enabled and when it is disabled, and the ideal value can be measured when the buffer is enabled.

In the data of adding 300Ω and removing C9, the error became large even when the buffer was enabled.
It is thought that this is because the Reference input impedance of the ADC is 18.5 kΩ, so the resistance is divided by the 300 Ω resistor added in series, and the ADC recognizes the VREF voltage as a voltage that is about 1.6% lower.

After all, a voltage drop occurs due to the balance between the input impedance of the ADC and the 300Ω resistance, and it is thought that this voltage is measured by the ADC.

To use in the differential voltage range I want to measure (Vref 2.4V input 0.4-4.4V), do not insert a series resistor at the input when using with buffer disabled, or run SYSGCAL to eliminate the error. I thought I had no choice but to do it.

Is my understanding correct?
Is there any other way to get rid of this error?

Hi Umezawa-san,

One thing we noticed is that the CMRR of the amplifier you are using is not very good (60 dB from 0 to 5V input). It might be worth checking if this is the issue.

There appears to be better CMRR with a limited input range (86 dB from 1V to 4V). Therefore, you can try reducing the level of the input signal to >1V and <4V to achieve better CMRR. If the error reduces in magnitude, then this is the likely error source.

Let me know if you are able to perform this test, and let me know the results

-Bryan

Hi Umezawa-san,

I am glad that you have found the source of your error, and that it has been removed.

if you have additional questions, please start a new e2e thread and we will be happy to support you

-Bryan