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LM98640QML-SP: 64MHZ we are not getting from TXCLk output pin

Saranraj Rajasekar
Prodigy 50 points
Part Number: LM98640QML-SP

Dear Team,

     In one of project We are using LM98640QML-SP ADC for Data Acquistion in which feeding 8MHZ I/P clock and we are using Quad lane mode & expecting 64MHZ LVDS TXclk from Output. But We are getting 154MHZ from TXCLK Pin.  

But In Datasheet they mentioned that  A differential clock is also output with rising edge transitions aligned within each data eye. Data rates for Quad Lane mode range from 40 Mbps, with a 5-MHz clock, up to 320 Mbps, with a 40-MHz clock. 

we are configuring the spi  registers also, and  what SPI Configuration data is required to get the 64MHZ xclock from TXclk pin  if i feed the 8 MHz I/P clock. 

Is tbere any configuration settings ?

Thanks in advance

Saranraj R

  • 0
    TI__Expert 4480 points

    Hi Saranraj, 

    Have you followed the below initialization setup as mentioned in the datasheet? 

    1. Power up supply voltages VDD33 and VDD18.

    2. Apply signal to INCLK.

    3. Write all configuration registers (ie. re-write the baseline configuration to the registers as shown in Table 5 through SPI). Be sure to set the INCLK Range (2x05) and Sample & Hold (0x06) for the INCLK frequency used. 

    If you have written these registers properly, but still observing the issue, can you do the following? 

    1.  Perform a register readout of all the device registers and share this file with us. 

    2.  Apply any fixed code test pattern on the channels and then share the oscilloscope waveforms of the following signals INCLK, TXCLK, TXOUTx, TXFRM. 

    This will help us quickly find the root cause of your issue. 

    Thanks,

    Karthik