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Original question:

ADC09SJ1300: using together with TDA4VM

ADC09SJ1300: about serdes data rate for FPGA selection

Jerry Chen
Expert 5110 points
Part Number: ADC09SJ1300

Hi team,

My customer would like to evaluate, when ADC09SJ1300 operates in high sampling rate as 1.3Gsps, what the data rate of the serdes will be. They will use four serdes lanes (L=4). This is to select a suitable low cost FPGA. They would like to know the max data rate for either JESD204B and JESD204C with L=4.

Thanks.

  • +1
    TI__Intellectual 1180 points

    Hi Jerry,

    JMODE15 will give you four lanes per channel, which will be all your lanes since you are using the single channel ADC. This is the most efficient mode for transferring data due to its encoding spec and packet formatting.

    It will give you about 1.3Gsps * 12 bits res * 66/64 encoding / 4 lanes = 4.02 GHz data rate. Even though it's a 9 bit part, it is set up the same as the ADC12QJ1300, which has 12 bits.

    JMODE13 and JMODE11 require higher data rates (4.06 and 5.2 GHz, respectively) because their 8B/10B encoding spec is less sufficient, but they aren't better in any other respect

    Thanks,

    Drew