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ADS127L11: External Clock votlage levels

Part Number: ADS127L11
Other Parts Discussed in Thread: TXU0101

Let's say I'm running the ADS127L11 with AVDD and IOVDD at +5V and AVSS at 0V and I want to provide CLK with the output from an external oscillator.

What are the acceptable voltage levels for the CLK pin for that oscillator output. Would they fall under the 'digital input' spec?

With my IOVDD and AVDD config stated above, could the chip conceptually receive a 3.3V oscillator output on the CLK pin, assuming the CLK input falls under a different voltage level category?

  • Hello Adam,

    Yes, the CLK input is defined as a digital input referred to IOVDD, and the voltage levels must meet these requirements.  Since the minimum input voltage for a valid logic high is 0.7*IOVDD, with IOVDD=5V, you need a minimum of 3.5V, which cannot be supported by 3.3V logic.  In reality, the part will still likely work at room temperature in the lab, but you could expect failures over temperature and part to part variations.

    If you need to support a 3.3V logic level CLK source with IOVDD=5V, then I suggest you use a voltage level translator gate, such as TXU0101 or similar.

    Keith Nicholas
    Precision ADC Applications