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Original question:

AFE7222: Test patterns synchronization, DDR sample output sequence

AFE7225: CMOS straight offset binary TX/RX?

Mike Neuman
Prodigy 140 points
Part Number: AFE7225

The docs cover DFS_RX and DFS_TX which seem limited to LVDS-only (DFS_TX is in 5.7 - LVDX TX INPUT INTERFACE REGISTERS, and DFS_RX is in 5.8 - LVDS RX OUTPUT INTERFACE REGISTERS).

Is there a CMOS equivalent? The documentation is lacking on CMOS equivalents. For example, PATTERN_SEL_RX for LVDS is in Register 0x337 (again section 5.8). However, if you want the same feature in CMOS mode, you use register 0x031, which is exclusively documented in 11 - QUICK GUIDE and not in the register listing.

Are DFS_RX/DFS_TX applicable in CMOS? If not, is there a CMOS equivalent register? 

Thanks!

  • 0
    TI__Mastermind 18095 points

    You are correct that the information on the CMOS register controls is not as detailed as the LVDS interface.  Many of the parameters useful for manipulating the serialized LVDS do not apply to the parallel CMOS interface.  Section 11 does indeed have some programming instructions useful for setting up the CMOS interface.  The default configuration is 2's complement.  It sounds like you are interested in the offset binary configuration and the appropriate register to select that option.  If this is accurate, we will track down the register command structure required to implement that feature.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 140 points

    Exactly correct. Thank you!