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DAC37J82EVM: dac37j82

Part Number: DAC37J82EVM

Hi,

At the evaluation board :DAC3XJ8XEVM,  we removed the transformer and try  to use the single ended output.

However, noticed that  there is a DC offset at the AOUTP and AOUTN.  

can you please help where I can adjust the DC offset??  

when I changed the offset at Dig Block2 and enable it,  there is no any changes at the output..

thanks

Li

  • Hi Li,

    Since the DAC output is DC coupled, there will a common mode voltage(DC offset at output of the DAC). if you don't want common mode voltage on the output you can put an AC coupling caps to remove the offset. This common mode is inherent to DAC's output architecture you cannot remove it with register wrties.

    Regards,

    Neeraj

  • Hi, Neeraj

    Thanks for the reply.  What I try to do is remove the dc offset inherent in the dac itself.  And in real application, I still need to induce a certain dc offset on top of the signals in real time as needed. 

    so, I plan to do the external offset compensation in the amplifier circuit.  The issue I encounter is that,  the dac inherent dc offset is not a certain number.  when power the evaluation board up, the offset is alot higher like over 300mA with 25Ohm load.  when I set it to sleep, the offset drop to about 36mV at P output and 28mV at the N output.  This means I can't compensate it by hw.  I saw there is a DigBlock2, there is a dc offset section, not clear how to use that.. can you please help share some info on those??

    Also can you please help share some doc about recommend interface circuit for this dac? if use with dc coupled, what's recommended and what specification the dac will be??

    thank you.

    Li

  • Hi Li,

    Here is the design which talks about DC coupling the DACs output 

    https://www.ti.com/lit/ug/tiduc44/tiduc44.pdf

    Regards,

    Neeraj