I got a question about SPI Operation in D/S 9.1.1.
It says that:
1. Use an SCLK that is phase coherent to CLK; that is, ratios of 2:1, 1:1, 1:2, 1:4, and so on. 2. Minimize phase skew between SCLK and CLK (< 5 ns).
2. Minimize phase skew between SCLK and CLK (< 5 ns)
The question is:
1. How can we make coherent SCLK when default internal clock?
When changing register to external clock from default internal clock, Settings sometimes would not be changed.