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ADS127L11: SPI Operation about CLK/SCLK

Part Number: ADS127L11

Hi team,

I got a question about SPI Operation in D/S 9.1.1.

It says that:

1. Use an SCLK that is phase coherent to CLK; that is, ratios of 2:1, 1:1, 1:2, 1:4, and so on. 2. Minimize phase skew between SCLK and CLK (< 5 ns).

2. Minimize phase skew between SCLK and CLK (< 5 ns)

The question is:

1. How can we make coherent SCLK when default internal clock?

 When changing register to external clock from default internal clock, Settings sometimes would not be changed. 

best regards,


  • Hello Yuto-san,

    There is no way to use a coherent SCLK when using the internal CLK.  This is only a recommendation to get best performance from the ADS127L11 when sampling AC input signals (typically a sine wave).  The internal clock is useful if you are measuring DC signals, and will provide full dynamic range performance in this case.

    The internal clock has a lot of jitter, and is not suggested when sampling an AC signal, especially if the data is processed through an FFT.  If you are measuring DC inputs, you can use the internal clock and do not need a coherent SCLK.

    Regarding your comment about changing the register setting from default internal clock to external clock, I am not certain why this does not work in your setup.  The ADS127L11EVM does this during initialization, and I have never seen a case where the clock did not switch correctly to external.

    Keith Nicholas
    Precision ADC Applications