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ADS1278-EP: The clock input and SCLK input

Xiang Maverick
Intellectual 750 points
Part Number: ADS1278-EP
Other Parts Discussed in Thread: ADS1278

According to a thread, the clock input and SCLK input should have the same clock source to avoid spurs in ADC spectrum (I do not understand what are spurs in ADC spectrum).

I have FPGA connected to the ADC. The clock input to the FPGA is a oscillator of 200MHz. The internal PLL can generate the clock of 13.5MHz, as well as a clock of 27MHz.  Can I connect the 13.5MHz to the ADC SCLK pin and the 27MHz clock to the ADC CLK input pin through FPGA IO?The datasheet says a low jitter clock should be used. Is the clock signal through FPGA IO the low jitter IO?

The datasheet says crystal can be used, but I do not know how to connect the crystal to a single clock input pin, In most cases, crystal should be connected to 2 pins of a device.

  • 0
    TI__Mastermind 36170 points

    Hello Xiang,

    Spurs in the ADC spectrum are any unwanted frequency components that are higher than the noise floor.  Below picture shows an example of frequency spurs highlighted in yellow.  These spurs will increase the noise in the ADC measurement, reducing the SNR.

    You can use the FPGA to generate the CLK and SCLK signals, but the clock source for the FPGA should be low jitter (most crystal based oscillators will work well).  However, most FPGA PLLs will introduce additional noise that may not work well in your system.  I suggest using a simple /8 divider inside the FPGA (instead of PLL) to reduce the 200MHz FPGA clock to 25MHz for the ADS1278 CLK, and another /2 divider to 12.5MHz for SCLK, for best noise performance.

    A third option is to use a separate oscillator to directly drive the CLK pin of ADS1278, and have the FPGA generate SCLK based on the 200MHz clock, but this will result in frequency spurs and increased noise (reduced SNR).

    An example of a suitable oscillator for the CLK input is the SXO53C3A071-27.000M.  These devices have digital buffers and generate a single CMOS clock output.

    https://suntsu.com/wp-content/uploads/2019/07/SXO53C-Series-1.pdf

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Intellectual 750 points

    I think if the clock input and SCLK input do not have the same clock source, the synchronization strategy of digital signal should be used across the 2 clock domain.

    But I do not understand why it will create spurs in ADC spectrum.

    Thank you

  • 0 in reply to Xiang Maverick
    TI__Mastermind 36170 points

    Hello Xiang,

    A small amount of energy from CLK and SCLK will couple into the ADC inputs, and due to mixing, can show up as a lower frequency signal that will pass through the digital filter and increase the noise floor.  

    This noise coupling is typically very small, but does show up.  Depending on your system requirements, this may not create a problem for you.  We recommend synchronization to get the very  best performance from the ADC, but in many cases, there will be other noise sources in the system that dominate and you may not need to go to these extreme measures.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Intellectual 750 points

    "show up as a lower frequency signal that will pass through the digital filter and increase the noise floor" Does the noise floor means the noise at ground?

  • +1 in reply to Xiang Maverick
    TI__Mastermind 36170 points

    Hello Xiang,

    In this case, I am referring to the total noise when the inputs are shorted to ground.  As an example, the measured results shown in Figure 6 of the datasheet may increase if the clocks (CLK and SCLK) are not synchronous with each other.

    Regards,
    Keith