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some help neeeded

Pedro Guerra
Prodigy 20 points
Other Parts Discussed in Thread: ADS5281

I'm working on a custom s-6 design where several ads5281 are being used.

To try out intermediate code I have ADS5282EVM, whichs has been succesfully connected to spartan 6 sp605 via FMC to ADC adapter adapting ideas and code from xapp866 & xapp774.

 

however, i'd like to try out richard's approach, which seems much less demanding in terms of clock buffers.

Richard, could you send me your code?

My email is: pedro.guerra@upm.es

 

has any one suceeded in implementing that in vhdl and setting the rigth ucf  constraints  for the S-6?.

Some guidance with working constraints would be greatly appreciated.

 

 

 

 

 

  • 0
    TI__Mastermind 29220 points

    Sent to the email address provided.

    Oh, and In that email i did not mention that no, we have not implemented that in VHDL, just Verilog.  And for the timing into the FPGA, the default tap delay settings for the IDELAY are set in the file defines.vh.  For the Spartan6, the delays of the IDELAY tap might be different than the Virtex4, and the prop delay through the clock buffer wil be different, so a different default IDELAY tap setting will likely be needed.  The Static Timing Analyzer in the Xilinx tool set will let you know if the defautl tap setting is correct ot not by whether there are violations in the timing constraints. 

    Regards,

    Richard P.