The TI E2E™ design support forums will undergo maintenance from Sept. 28 to Oct. 2. If you need design support during this time, contact your TI representative or open a new support request with our customer support center.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38J84: DAC38J84 device initialization and sysref configuration Consult

Part Number: DAC38J84

Hi Teams,

I'm evaluating DAC38J84 according to SLAA696 DAC38J84 device initialization and sysref configuration. However, I came across several problems. Can you help me to solve these issues?

1, SYNCB will be pulled low, after step 12. This results into the reconnecting of communication. FPGA will continuously send the reconnect request.

2, Can you help to explain the step 14 to me, I don't understand this step.

Thanks and BRs.

Marsh

  • Hi Marsh

    1, SYNCB will be pulled low, after step 12. This results into the reconnecting of communication. FPGA will continuously send the reconnect request.

    Correct. With SYNCB in logic low, FPGA should be sending K28.5 character per JESD204B standard

    Step 14 basically said that the SYSREF will initialize the JESD204B state machine, and trigger the SYNCB to be logic low to trigger the SYNC reconnect request.

  • HI Hsia,

    Thanks for your reply. So what’s the purpose of step13 and 16?  Will “clear” in step13 affect the “check” in step16?

    BTW, What’s the format of the code (Page 56 in Datasheet)? Source code or complement? with 0xFFFF or 0x0000 input, the output comes out Vcm both.

     Thanks & BRs,

    Marsh

  • step 13 and step 16 is just checking for any errors during link-up

    You can find the format of the code by searching for "two's complement" or "offset binary" configuration in the register map

    By the way, please advise your project. I am curious to your project on the DAC38J84 family.