I'm using the ADC3660 to sample some data at 25 MSPS. I'm trying to get the command/clock interface running with my FPGA, and I can reliably write/read the registers in the ADC. I'm trying to use the following settings.
- Sample rate: 25 MSPS
- Output Mode: 2-wire decimation bypass, 16 bit resolution
- Sample Clock: Differential
- Voltage Reference: External 1.6V
I'm running the following function with the soft core processor in my FPGA. write_a2d_spi(destination,value) write's "value" into the "destination" register in the ADC. I have confirmed that I can read back the values that I wrote, so I'm confident I'm commanding it properly.
u32 configure_ti_a2d(void)
{
// refer to TI 3660 datasheet, section 8.3.5.4.1 (Configuration Example)
write_a2d_spi(0x7, 0x4b); // 16-bit, 2-wire
write_a2d_spi(0x13, 0x01); // load efuse step 1
usleep(1000); // wait 1 ms
write_a2d_spi(0x13, 0x00); // load efuse step 2
write_a2d_spi(0x0A, 0x7F); // configure CMOS output buffer step 1
write_a2d_spi(0x0B, 0xEE); // configure CMOS output buffer step 2
write_a2d_spi(0x0C, 0xFC); // configure CMOS output buffer step 3
write_a2d_spi(0x18, 0x10); // enable DCLKIN
write_a2d_spi(0x1B, 0x08); // select 16-bit resolution
write_a2d_spi(0x1F, 0x50); // enable DCLKIN and DCLK output Buffer
return 0;
}
I haven't implemented any logic to decode the data coming from the dA5/6 and dB5/6 channels, but I see data on them and I see what I would expect from DCLK and DCLKIN with my logic analyzer (both 100 MHz). However, FCLK seems to be high for half a clock longer than expected. I verified this on the oscilloscope which measures FCLK duty cycle at ~62%.
Theoretically, as long as a new word starts on the rising edge of FCLK, I can just count DCLK and use that to keep track of the start and each data word, but I'm wondering if I did something wrong in the configuration of the ADC to change the duty cycle of FCLK. I'm trying to read back a constant test pattern with my logic analyzer, and I'm only seeing the test pattern in the first 16 bits of every FCLK cycle, and then the next 16 bits seem to be something totally different, so that leads me to believe something isn't set up right.
Is there a command or setting I can send to change the FCLK duty cycle to 50%? Is this a sign of other issues?
