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ADS1287: DRDY signal in continuous-sync mode is different from expected.

Part Number: ADS1287

Hello !

Please advise.

I am trying to synchronise three ADS1287 under the following conditions, but the DRDY outputs are output at different timings.

My image is that all DRDY will output at the same timing when operating in Continuous-sync mode, but is this a misunderstanding? 

Currently, the output of DRDY seems to be determined by the timing of initialising AD.

-  AD_CLK and SYNC divided from a common clock.
  AD_CLK: 819.2 kHz
  SYNC: 100 Hz
  Sampling: 100 sps

- The rising edge of SYNC is synchronised with the falling edge of AD_CLK.

- The same AD_CLK and SYNC are used for all three channels.

- The setting is Continuous-sync mode.

- However, the DRDY timing of each channel is different.

- The conversion result for each channel is OK.

- It would be perfect if the phases of each CH were aligned.

Thank you,

Akihiro Yamazaki

  • Hello Yamazaki-san,

    Have you confirmed if the devices have ever resynchronized at the same time? In other words, have you ever forced all devices to resynchronize at the same time so that the conversions between all devices can all happen at the same time?  

    To summarize SYNC, SYNC can toggle and then it will initiate a count inside the device. if the count value from one rising edge of SYNC matches the count value at the next rising edge of SYNC nothing happens as the system is in sync.  However, if the count values (which a clocked at CLK rate) do not match up the system runs the sync process. Note that SYNC does not have to match the phase of /DRDY.

    As a result, it is entirely possible for each device to start conversions at different times as a device powers up and there's delays between putting the devices into the correct data-rate. In this case, the SYNC never triggers a resynchronization because all of the SYNC timing always lines up (with different phase shifts for each of the /DRDY). 

    I would recommend pulsing SYNC in continuous mode that is less and not equal to an integer of /DRDY. This should cause all ADCs to resynch at the same time and all conversions should start at the same time. Because the output data looks good and timing between SYNC and DRDY seems constant, it sounds like SYNC is doing its job correctly, its just that the conversions never started at the same time..

    Let me know what you find.

    Best,

    -Cole

  • Hello Cole,

    Your explanation has almost made sense to me.
    The relationship between SYNC and DRDY seems to be stable and properly synchronised. I am relieved.

    Thank you very much for your detailed explanation.

    Yours sincerely

    Akihiro YAMAZAKI