ADS8320: Output disturbed

Tania GALLET

Part Number: ADS8320
Other Parts Discussed in Thread: SN74LVC4245A

Hi,

I have some troubles with the component ADS8320. I develop an electronic card to take measurements. In this card there are 2 ADS8320. Their input are different but their output are connected.

The problem is that the signal after the connection is disturbed the low level is egal to 2.2V and not 0V.

I read the datasheet but I don't understand why I have this problem.

Thanks.

over 2 years ago

0 Tom Hendrick over 2 years ago

TI__Guru**** 174576 points

Hi Tania,

Welcome to our e2e forum! When you say 'their output are connected' do you mean that the two DOUT (pin 7) are tied together? Can you also explain what you mean by 'the signal after the connection is disturbed' means? Can you provide a schematic and/or layout? Do you have screen captures of the SCLK, DOUT and /CS lines?

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

Hi Tom,

Thanks for your response.

As you can see the two DOUT are tied before the component SN74LVC4245A (used to change 5V / 3.3V).

I want a low level smaller than 2V but in my case the low level is egal to 2.2V.

Thanks,

Tania

0 Tom Hendrick over 2 years ago in reply to Tania GALLET

TI__Guru**** 174576 points

Hi Tania,

I believe you are experiencing bus contention. The SN74LVC4245 has a DIR pin that selects the direction of data between the A and B side of the chip. The /CS and SCLK come from your RPi while at the same time the DOUT comes from the ADS8320. So, you have information that is trying to be transferred from both A and B bus at the same time, and that won't work. You can only go from A to B or from B to A depending on the logic applied to pin 2 of the SN74LVC4245. If you have to run the ADS8320 at 5V, there are single gate level translators that you could use. Look for our 'Little Logic' series of devices.

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

Hi Tom,

I know how the SN74LVC4245 works. To convert the /CS and SCLK, I use a other solution :

So my problem is not here.

Tania

0 Tom Hendrick over 2 years ago in reply to Tania GALLET

TI__Guru**** 174576 points

OK - Can you provide a complete schematic? Do you have a 4CH scope that can show /CS, SCLK and the two DOUT's?

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

0 Tom Hendrick over 2 years ago in reply to Tania GALLET

TI__Guru**** 174576 points

Thank you Tania,

Can you provide the O'scope (or logic analyzer) plots I asked for?

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

I have

/CS and SCLK on RaspPI

The two Dout (yellow) and SCLK

I have only a 2CH scope

MISO and SCLK on the RaspPI

0 Tom Hendrick over 2 years ago in reply to Tania GALLET

TI__Guru**** 174576 points

Tania,

Take a look at Table 1 in the ADS8320 datasheet (page 14) and Figure 29 (page 24). Change you clock around so that it is in a low state when its not driving DOUT. From there, please try to isolate one of the DOUT pins (lift pin/cut trace, whatever is easiest) and let me know what you see.

0 Tania GALLET over 2 years ago in reply to Tom Hendrick

Prodigy 10 points

Ok, so this is what I see with just 1 DOUT

yellow = CS on the RaspPi

blue = MISO on RaspPi

I cut DOUT0 and let the same clock, and it works.

0 Tania GALLET over 2 years ago in reply to Tania GALLET

Prodigy 10 points

In fact, I need the intern structure of the output of the ADC.

0 Tom Hendrick over 2 years ago in reply to Tania GALLET

TI__Guru**** 174576 points

OK then! Making some progress!

The scope trace above is from the 'B' side of you level shifter - what do SCLK and DOUT look like at the ADS8320 side? If you probe the two DOUTS, you probably have good data at each one. Probe the two /CS pins and make sure that they are not both active at the same time. You Rasp Pi should have the ability to set the SPI function to 'Mode 0', where SCLK dwells low while inactive and data is read on the rising clock.