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ADC10080: Conversion Latency Inquiry

Part Number: ADC10080

Hello Team,

My customer would like to know if the conversion latency applies to all samples? Is there a latency of 6 clock cycles for every digitized output in relation to the corresponding input sample? Or is there an initial latency until the first valid sample and then no latency between sample at the input and the digitized output? In other words, can you explain the process of analog to digital conversion from input to output? For example, can you explain the path an input sample takes each clock cycle until it reaches it's digitized output ? Thanks


  • Hi Renan,

    The latency is always present inherently in the converter architecture. The latency merely means that the output data is 6 clock cycles ahead at any given point in time because that is how long the entire conversion process takes. See below screenshot taken from page 9 of the datasheet:

    Also see the functional block diagram, also from the datasheet, that outlines the various stages of this ADC's pipeline conversion process:

    Feel free to post a separate question if the customer has more specific questions about stages or latency.