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ADC12DJ5200RF: ADC12DJ5200RF Background Calibration Mode

Joseph Pathikulangara
Prodigy 180 points
Part Number: ADC12DJ5200RF

i am using the ADC12DJ5200RF at 10.24 Gsps in single channel mode.

when Background Calibration Mode is enabled, and when the spare ADC core switches in, the data is occasionally corrupted. some lane gets misaligned. after a few cycles of ADC core switching, sometime the data alignment comes back. but eventually many lanes go out of whack.

in Foreground Calibration Mode, (there is no core switching) the data is stable and good for days.

  • 0
    TI__Mastermind 20541 points

    Hi Joseph,

    Can you please share how the data looks like when it is "BAD". Can you please let me know if you are using the ADC EVM or is the ADC on your board? This is a strange behavior. I do want to mention, the ADC cores swap in background calibration there is a small glitch which happen which is also mentioned in that datasheet.   

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 180 points

    Thanks Neeraj. i was working off the April 2019 datasheets. about to go through the latest one. apologies for potentially a non-issue.

    the board is own design. and i was turning on the background cal while initializing the ADC which was probably a bad idea.

    however, if i turn on background calibration when the programming is complete (and JESD lanes/data is correctly locked/decoded), the so called glitch mentioned in figure 6-143 actually translates into one clock (40 samples) delay in the signal.On a few occasions i have noticed that this transition occurs as a two step process. For instance 7 lanes switch to a delayed state while the remaining lane switches a bit later. effectively producing two glitches. and the sample data in between the two events is suspect.

    and once this 40 sample delay occurs, then things are stable.

    the two step transition could be an artifact of the JESD receiver...

    in any case, "This resolved my issue"

    thanks and regards,

    joseph