Other Parts Discussed in Thread: CDCE6214
SBAU360.pdf describes the HW modifications needed for onboard clocking.
Figure 5-3 shows the addition of a pulldown resistor on the clock generator's PDN line.
If I understand CDCE6214 functionality correctly, pulling PDN low mutes the differential clock outputs
(defeating onboard clock generation).
Shouldn't R69 be left DNI?