ADC081520QML Calibration, Data Rate, I,Q Channels, Extend-mode

Madhukiran (Madhu) Panabakam

Prodigy 170 points

Hello,

Trying to configure the ADC in Extended-Control Mode with Pin 41 set to low. As you can see in the attached image.

Data rate at 250msps, with CLK+/-(pin 18 and 19) set to 250MHz.

Goal is to send the data on VINI+/-(pin11 and 10) and receive data on DId0+/- thru DId7+/-

and send data on VINQ+/-(pin22 and 23) and receive data on and DQd0+/- thru DQd7+/-.

In Extended -Control Mode, while I am writing the registers

Do I have to set Pin15,26,14,and 30 to 'Z' ? Is this must ? what happens we have leave them driving.

Can please comment on my register setup for calibration for above datarate setup:

x"001" & x"1" & x"B7FF"; --Header & Reg Address & Reg Data(ConfigReg)
x"001" & x"9" & x"03FF"; --Header & Reg Address & Reg Data(ExtConfigReg)
x"001" & x"2" & x"007F"; --Header & Reg Address & Reg Data(IoffsetReg)
x"001" & x"A" & x"007F"; --Header & Reg Address & Reg Data(QoffsetReg)
x"001" & x"3" & x"E07F"; --Header & Reg Address & Reg Data(IfullscaleReg)
x"001" & x"B" & x"E07F"; --Header & Reg Address & Reg Data(QfullscaleReg)
x"001" & x"E" & x"00FF"; --Header & Reg Address & Reg Data(ClockPhasFineAdjustReg)
x"001" & x"F" & x"007F"; --Header & Reg Address & Reg Data(Int/CoarseAdjustReg)
x"001" & x"0" & x"7FFF"; --Header & Reg Address & Reg Data(CalibReg)(CAL='0')

wait for 1280 cycles and then setup the following register
x"001" & x"0" & x"FFFF"; --Header & Reg Address & Reg Data(CalibReg)(CAL='1')

One more question on Input Select Bit, it is kind of confusing. Can you please let me know whether am i setting the following bit correct for the setup I am using.

IS: Input Select. When this bit is set to 0b the I- Channel input is operated upon by both ADCs. When this bit is
set to 1b the Q- Channel input is operated on by both ADCs.

Thank you in advance.

over 1 year ago

0 Madhukiran (Madhu) Panabakam over 1 year ago

Prodigy 170 points

Correction to the above request.:

I was expecting to receive the signal on DI0+/- thru DI7+/-

and DQ0+/- thru DQ7+/-

NOT ON DId and DQd.

With the following setup I should be see 250MHz clock on pin81,and82, but I see 125MHz.

What am I doing wrong ?!

0 jim s over 1 year ago in reply to Madhukiran (Madhu) Panabakam

TI__Guru* 91947 points

MK,

We are looking into this.

Regards,

Jim

0 Madhukiran (Madhu) Panabakam over 1 year ago in reply to jim s

Prodigy 170 points

Jim,

Thank you for your prompt Response.

Basically, I would like to run the ADC in SDR mode, 1:1 Demux Non-DES Mode.

CLK+/- at running at 250MHz and expecting DCLK+/- to be 250MHz

VINI at 250msps, and expecting recevie on DI Channel at 250msps

VINQ at 250msps and expecting receive on Dq Channel at 250msps

Thanks

0 Drew Pierpont over 1 year ago in reply to Madhukiran (Madhu) Panabakam

TI__Intellectual 1180 points

Hi MK,

I'm looking through the register values and what you currently have running. Just to clarify, you are still seeing 125 MHz at pin 81/82 despite setting the registers for 1:1 Demux, Non-DES and SDR mode, correct?

Thanks,

Drew

0 Madhukiran (Madhu) Panabakam over 1 year ago in reply to Drew Pierpont

Prodigy 170 points

Hi Drew,

That is true.

Thanks

0 Drew Pierpont over 1 year ago in reply to Madhukiran (Madhu) Panabakam

TI__Intellectual 1180 points

Hi MK,

Thanks for your continued patience. Could you please let us know what supply voltage you are using into VA? This may determine whether Pin 4 is triggering DDR against your will. I'm not sure if this would matter if you are already keying in Extended Control Mode, but I am still investigating that as well as the high-impedance question you asked.

Thanks,

Drew

0 Madhukiran (Madhu) Panabakam over 1 year ago in reply to Drew Pierpont

Prodigy 170 points

Hi Drew,

We are using 1.9V for VA and VDR.

Thanks

Madhu

0 Drew Pierpont over 1 year ago in reply to Madhukiran (Madhu) Panabakam

TI__Intellectual 1180 points

Thanks MK, this is helpful.

Could you set the data rate to DDR and recheck pins 81 and 82? We want to see if there's an issue with that write and if it's taking the SDR command. Please check that, and then set it back to SDR and check again. That will help us eliminate at least one more potential issue.

Thanks,

Drew

0 Madhukiran (Madhu) Panabakam over 1 year ago in reply to Drew Pierpont

Prodigy 170 points

Thank you Drew.

How do you want me to set that ? Do you want me write to the config register ?

What value do you want me to write into what register ?

I just want to make sure that I am writing the right value as you expect it to be.

Thanks

Madhu

0 Drew Pierpont over 1 year ago in reply to Madhukiran (Madhu) Panabakam

TI__Intellectual 1180 points

MK,

Write B3FF to the Configuration Register, allow some time to ensure the values change, and then write B7FF to it. Check pins 81/82 again. If you are still getting 125 MHz, try writing the register to its default (B2FF) in the same manner followed by B7FF and probe the outputs one more time. Please let me know what you find.

Thanks,

Drew

0 Drew Pierpont over 1 year ago in reply to Drew Pierpont

TI__Intellectual 1180 points

Marking Resolved due to discussion moving online and customer finding workaround, closing thread.

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ADC081520QML Calibration, Data Rate, I,Q Channels, Extend-mode