ADS8168: Verilog or VHDL simulation model available?

Brett Hansmeier said:

Is a Verilog, SystemVerilog, or VHDL simulation model available for the ADS8168? That would be helpful to speed up debug and do a more thorough verification of my interface RTL.

This is an evergreen question.

What TI (and Analog Devices, and the others) fail to understand is that FPGA engineers really need to verify their designs. To do that, we need models that are correct. We can certainly create our own models from the data sheets (and we do; I have a good couple dozen right now) but the problem is that the assumptions we make in writing our design HDL are the same as those we make to create the model. And if those assumptions are wrong, then we waste time in the lab verifying operation and correctness.

Come on, TI, it's mid 2022, and your high-speed converters are meant to interface with an FPGA. Models we can trust are mandatory.

At least the response was not, "We have IBIS models ..." -- I've actually been told that by a tech support person.

I did get it working eventually by using lots of ILA builds and lab debug time - not the method I prefer. A simulation model would have saved me a lot of time and likely produced a far more robust RTL design.