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ADC3663: Noise spikes from A/D

Part Number: ADC3663
Other Parts Discussed in Thread: THS4551

I am testing my prototype board with ADC3663. The AD differential driver schematic follows the recommendation of datasheet and EVM board of ADC3663, as attached. The input is a single-ended 2MHz pure sinusoidal signal, but the output of THS4551 and the input to the ADC3663 has large spikes with the same frequency of sampling rate (50MHz).

Clean 2MHz single ended sinusoidal signal input 

Output at THS4551 and Input to ADC3663 with spikes

After I read several articles (eg. High speed sampling ADCs by Walt Kester) , it seems these spikes come from ADC kicking back during sampling because ADC3663 is an unbuffered ADC. After I removed R152 and R159, the spikes disappeared at output of THS4551, which proves it is indeed from ADC3663 kicking back. At the rising edge of sampling clock, ADC internal switches change mode from track to hold which introduces ~1mA current within several ns into output of differential driver. This results into 100mV spike (assuming 100 ohm total impedance).  Then at the falling edge of sampling clock, ADC internal switches change mode from hold to track which introduces 5mA current within several ns due to charging of ADC cap, resulting in spikes again. So it requires differential driver to be able to quickly charge the ADC cap before the next rising sampling edge. So the close loop gain of differential driver needs to be higher than sampling rate. But this requirement is then conflicting with anti-aliasing LPF because LPF needs to be at least less than half of the sampling rate? Another problem is from the scope display, the recommended driver schematic and differential driver seems not fast enough drive the input of ADC to settle down to real signal level (with 2MHz sinusoidal and also DC level situation).

Spikes with input of 0V; from this, it seems that driver can not fully settle to real signal level during sampling

Is my understanding correct and any suggestion to solve the issue? Thanks.

  • Here is the schematic 

  • Hi John,

    This is correct, the ADC will kickback charge injection back onto the analog inputs of the ADC from the internal sampling switch of the ADC.

    This is very common trait for these types of unbuffered ADCs. Keeping the 10ohm series resister near the ADC will help with this. Adding an additional filter cap to ground after the 10ohms will also help.

    However, the schematic you provided should be fine in order to move forward.



  • Hi, Rob:

    Thanks for the reply. As you suggested, I put a 68pF cap at the A/D on each line to GND and the sampling clock spike amplitude are reduced. But somehow with GND input, the AD values variance is increased from ~5 LSB to ~15 LSB which should be reduced instead. I will try to make more adjustments to figure out why. Your recommendation of moving 10 Ohm serial R closer to AD and adding cap to GND make sense and I will implement them in the next revision of the boards.