Other Parts Discussed in Thread: AFE5848
Dear TI Support/Expert,
I am using AFE58JD48 in X80 mode, try to implement 16 JESD lanes to support 4 AFE58JD48 chip. from TI chip side is straightforward. LMF = 4X16X8. We use Intel Arria 10 development kit as the receiver.
the problem is on the Intel JESD204B IP. per data sheet, it claims that each lane has 32 bits internal data path. so I have to set the receiver LMF = 4X16X4( per lane). the receiver side only support X40 mode. in this case, the only problem is the JESD204B protocol. the transmit side will send out 8 octets/lane per frame. the receiver side will break the 8 octets frame into two 4 octets in two clock cycle. in JESD204B domain. how critical the frame package is? will the receiver be able to recover the whole frame?
if Intel IP only correspond 32 bit data width per each Jesd204B lane, Do I have to use 32 JESD204B lanes to implement 64 ADC channels( 4 AFE58JD48)? is there a way to manipulate the LMF perimeters and the lane rate over the link rate to make 16 Jesd204 lane work?
Here are the links I posted on the Intel community. I am still waiting for some suggestion.
Jesd204B IP force F = 2 when use phy only wrapper - Intel Communities
Fundamental question about Jesd204B, Lanes VS ADCs - Intel Communities
hope I can get some suggestion from the JESD204B application expert.
Appreciate your help.
David
