Hi team,
A question from one of our customers:
The LM98725 is 8bit*2 in CMOS output format, the customer docks a chip that is an 8-bit DVP interface, but the software does not allow sampling eight bits MSB and eight bits LSB on the positive and negative edges of the LM98725 CLKOUT. Sampling can only be performed for a single-edge transition, that is, only a rising edge or a falling edge sample can be sampled.
I would like to confirm that the INCLK and CLKOUT of the LM98725 are the same frequency and phase signals? If so, can the customer output a clock with frequency 2*INCLK and a clock with frequency INCLK as CLKOUT and INCLK for LM98725 respectively, from the CPU? That is, only the rising edge of the 2*CLKOUT signal is sampled. This is shown in the following figure
Best Regards,
Amy Luo