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ADS8864: Conversion time and bus with multiple devices

Sunset
Genius 13535 points
Part Number: ADS8864

Hello Team,

can you clarify the following points:

  • Tsample is defined by tconv_max and tacq. Tconv_max is 1300ns so that 1200ns are left for tacq (which is at the same time the minimum for tacq) to reach 2500ns tsample (400kSps).
    • tacq = 1200ns = td_cnv_do + 16 tsclk + margin -> tacq = 12,3ns + 16x62,5ns + margin @ 16MHz SPI SCLK
      • -> meaning that with a SPI SCLK of 16MHz the timing constraints are reachable for 400kSps if you prolong tacq to 1200ns
    • Is that correct?
  • As long as DIN and CONVST are high other ICs on the SPI bus can use SCLK and DOUT without any conflicts, right? So the ADS8864 doesn’t react on any SCLKs and leaves DOUT on high impedance during that time? So I could communicate with other ICs while DIN and CONVST are high.
  • DOUT becomes high impedance after the 16th SCLK → meaning that CONVST can be left low until the next conversion cycle and other ICs can use SCLK and DOUT in the meantime without any conflicts?

 

Thanks,

SunSet

  • +1
    TI__Mastermind 24940 points

    Hello, 

    1. Yes, your understanding on the timing is correct. 

    2. The device has six modes of operation. It seems you are interested in the using 3 wire mode without daisy chain nor busy indicator. To accomplish this, DIN needs to be high at CONST rising edge. If DIN is hardwired to be high, then the device will always operate in 3 wire mode.  When CONVST rising edge, the SCLK and DOUT go into high impedance mode, and, as you noted, can be operated without affecting the ADS8864. Alos, DOUT does go into high impedance mode after 16 SCLK or CONVST rising edge, whichever comes first. 

    3. your last point is incorrect. with CONVST is low, and 16 sclk have passed, DOUT will enter high impedance mode, but not SCLK, this pin will still be active. I would not suggest this mode of operation, nor can I state how the device will respond if more SCLK are provided after the initial 16 while CONVST is held low. Thus it is not suggested to operate SCLK while keeping CONVST low. 

    Regards

    Cynthia