I am using an FPGA (Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit (xilinx.com))to close a 25Mhz power converter and would like a high speed ADC for a voltage mode control loop. Is it possible to get the ADC's digital out put in under 1/25M to the FPGA? And/or what is the fastest I can get an ADC reading to an FPGA, from the TI product lines. Would love a recommendation and would like to buy an EVM board accordingly.
Appreciate the help,
Patrick
Hi Patrick,
Do you have any constraints on ADC selection? Sample rate, input bandwidth, resolution, # channels, power consumption, output interface (LVDS/CMOS)?
One device family which may be worth looking into is the ADC3663 (65MSPS, dual channel), ADC3662 (25MSPS, dual channel), ADC3663 (65MSPS, single channel), or ADC3662 (25MSPS, single channel). These devices have a few options for output data rate which should achieve your target of incoming sample target of greater than 25MHz. These output data formats are referred to as 2-wire, 1-wire, and 1/2-wire mode (dual-band specific) allowing for flexibility in the data clock (DCLK). The below figure shows how two consecutive 16-bit samples can be transmitted using either method. 2 differential pairs (2-wire mode) or 1 differential pair (1-wire mode) within the same time period (FCLK).
Regards, Chase
Thanks Chase for getting back to me,
I don't have any power constraints.
I only need 1 channel.
The bandwidth is some what flexible, but greater than 250Mhz is preferred
The output interface is not limiting, I have a lot of flexibility with my FPGA. JESD204B is also an option.
I really appreciate your options and ADC 3663 looks to be the highest sampling rate with the dual channel output, (also was looking at the ADC 3664 for its 125MSPS). Just curious the RF ADCs that Xilinx recommends ( ADC12J4000) would not work due to their higher latency of 10s of clock cycles right?
Last question,
I just want to make sure I have the clocks straight. There is a sampling clock, a frame clock and a data clock. The sampling clock runs intuitively at the sampling frequency, the frame clock is how long a frame of data is, the data clock is for each bit. I didn't notice a data clock min or max in the datasheet, but it looks to be faster than the sampling clock. My xilinx can run at 800Mhz, could the data clock run that fast or is there a limit you recommend? I also checked the charts out at the bottom of the datasheet, so I think it would work..
