**Part Number:**AMC1106M05

**Other Parts Discussed in Thread:**TMS320F28388D,

Hello,

I am struggling with the signal timing of the AMC1106M05 delta sigma modulator, together with the TMS320F28388D. In principle what I have is this:

The timing diagramm will look like this:

For evaluating that requirement for the hold time is fullfilled, I take the following values from the datasheets of AMC1106 and TMS320F28388D:

t_{H,AMC1105 }= 3.5ns (Hold time of data output after rising edge of clock input)

t_{S,TMS320 }= 1*PLLRAW + 5ns = 10ns (Required hold time, SDx_Dy wait after SDx_Cy goes high)

The hold time of the signal chain is calculated by the following formula:

t_{H }= t_{P,ClkBuf }+ t_{P,BrdDly }+ t_{H,AMC1105 }> t_{S,TMS320}

If I assume that clock buffer is quite fast (hard to find a slow clock buffer), or maybe even not in the signal chain, then the delay is t_{P,ClkBuf }= 0ns ... 1ns. Further the delay caused by the PCB signal transmission is in the range of t_{P,BrdDly }= 1ns ... 3ns. The formula will result in:

t_{H }= 0ns_{ }+ 1ns+ 3,5ns = 4,5ns, and this is unfortunatley lower than 10ns.

In other words this would mean, that at the moment the TMS320F28388D is sampling the data, it is not assured that the AMC1106 is holding the data output stable long enough.

Is my implementation correct? Do I have a mistake in thinking somewhere?

Best regards,

Michael Kettler