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DAC3171: About data latency

Yorihiro Sato
Prodigy 20 points
Part Number: DAC3171

Hi,I have a question about latency.

We have created a prototype board and confirmed the operation of the DAC.

The clock operates at 200MHz, the FIFO is disabled, and under that condition, a delay of about 100ns can be seen between input and output.

Is this the correct value? Also, can the delay be reduced any further?

And what does "Digital latency" in the datasheet mean?

  • 0
    TI__Guru* 91947 points

    Yorihiro,

    The delay you report is also based on the FIFO_OFFSET setting you are using. With the FIFO_OFFSET set to the default value of 0x100, I would expect the delay to be around 65ns. Try lowering this value if possible to reduce your latency. Using a faster sample clock will also lower the latency.

    Another option to reduce latency is to bypass the FIFO. When the FIFO is bypassed, the DACCCLK and DATACLK must be aligned or there may be timing errors; Per the data sheet though, this mode is not recommended for actual application use.

    Digital latency is the delay caused by the digital logic used such as the FIFO logic, programable delay logic, and de-interleaved logic. This does not include any digital to analog conversion delay.

    Regards,

    Jim