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ADS5296A: Timing Specification not clear from data sheet

David Wende
Intellectual 630 points
Part Number: ADS5296A

I am looking at the setup and hold times for the case of 10x serialization in data sheet dated October 2013 (SBAS631).

On the one hand, the table on page 7 shows Tsu = 0.2 and Th = 0.16. These are defined in the figure 3.

Does this refer to a specific combination of clock / data delays (tables 68 & 69), or is it a baseline which must ALWAYS be adjusted by the specific delays chosen in these tables?

Another unrelated question.

Are the test patterns functional also in interleaved mode?

Thanks

David 

  • 0
    TI__Expert 4684 points

    Hello David, 

    I'm notifying the relevant engineers for their visibility on this. 

    We'll have a response for you within 48 hours. 

    Kind regards,
    Nick Zahabizadeh

  • 0
    TI__Expert 4740 points

    Hi David, 

    Sorry for the delay. 

    The setup-hold numbers you are referring to is only for 10x serialization with decimation filter disabled. Please refer to Tables 1-5 for a more exhaustive timing information. All these timing specifications are taken with output clock and data delay settings of 0 ps. That is, for DELAY_DATA_R = DELAY_DATA_F = 00; DELAY_LCLK_R = 100, DELAY_LCLK_F = 011. 

    The test patterns are indeed functional in interleaved mode. But the dynamic test modes (ramp, toggle, or PRBS) increment in Fs/2 since each individual ADC (1 out of 8) is running at Fs/2. 

     

    Thanks,

    Karthik