Other Parts Discussed in Thread: ADC12DJ3200
We are using ADC12DJ5200 as a drop-in replacement of ADC12DJ3200 because we like to run at higher rate or Fs.
Our current FPGA project is in JMODE0/2 at Fs = 1600MHZ so Fbit = 6400Mbps. The rxlink_clk = 160MHz (or 6400/40)
The FPGA project was derived from TI Arria10 + ADC12DJ3200 JMODE0 Design Firmware — SLAC748.ZIP
I got ADC12DJ5200 work with the current FPGA project so no question about JMODE0/2.
However i could not get link up nor device aligned after changing to JMODE5/7.
Where Fbit = 6400Mbps so Fs = 2560MHz as R = 2.5. The rxlin_clk = 160MHz as the Fbit is the same.
Were they right?
I changed F = 1, S = 4, N= N' = 8 and K = 20 for the FPGA IP core, while L and M stay.
Did I miss anything?
Obviously, L and M definitions for the IP core configuration differ from what's in the ADC datasheets.
The L = 8 and M = 2 for the FPGA IP core configuration from Arria10 + ADC12DJ3200 JMODE0 Design Firmware
Which is for JMODE0/2.
So I like to know what would be the proper values of L, M, K, F, S etc. for JMODE 5/7 and JMODE11.
Hope to hear from you ASAP. Thanks a lot.