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ADC34J23: ADC34J23 Driving Circuit Design

Part Number: ADC34J23

Hi,

I'm using ADC34J23 in my design. The target frequency is 327MHz, so I adopted the circuit design for High Input Frequency(Fin > 230MHz) in the datasheet(Figure 206).

However, the ENOB of the actual product is very bad, and I found the input signal gets so much noise at the resistor just before the IC input pin(10Ω resistor in Figure 206) using a differential oscilloscope.

I've been investigating the cause and realized the circuit design in the datasheet is a little different from the evaluation board.

There is another part(25Ω resistor, 10pF capacitor, 56nH inductor) between the 10Ω resistor and the IC input pin on the evaluation board for high input frequency.

Why are they different? Does this difference cause noise to an input signal?

  • Hi Hiroaki,

    This is just an extra safety measure to help resonate out the internal parasitics of the ADC. Even though ADC datasheets will show a close estimate on the input resistance and capacitance for a device, the input capacitance can change due to environmental factors, board layout, component selection, etc. Circling back to my first statement, this external RLCR termination is to help with the parasitic capacitance of the ADC input, which should help to marginally reduce the analog input signal noise. Is it okay to post a selection of your ADC front end schematic here for us to take a look at? Also, what is supplying the 327MHz input tone?

    Regards, Chase

  • Hi,

    Thanks for the clarification.
    I attached the front-end schematic. If you need more detail, let me know.
    I am supplying the input signal with the function generator in Tektronix.



    Regards, Hiroaki

  • Hi Hiroaki,

    The frontend input network looks fine.

    The signal generator that you are using will not be sufficient enough to yield the datasheet performance of the ADC. The ENOB will be bad you inidcated above.

    Can you find a signal generator that provides a pure CW tone? Some examples include: HP8644B, R&S SMHU, R&S SMA100A or B.

    For more testing advise on ADCs, you can review the following application note: www.analog.com/.../AN-835.pdf

    Regards,

    Rob

  • Hi,


    The function generator can provide a CW signal.

    I tested with HMC-T2100 too, but the result was the same.
    I removed the 10Ω resistors in the above schematic and checked the signal on the solder pad where they were.

    It was a very clear signal, but I got so much noise again when I returned the resistors.

    Do you have any idea about this situation?

    Regards, Hiroaki.

  • Hi Hiroaki,

    I have a few requests,

    Can you send us the data you are capturing from the ADC? Are you sampling at 80MSPS? What is supplying the clock to the ADC? As Rob hinted at, these devices are characterized using the best equipment available to limit the impact of additive noise which will show the limitation of the ADC itself. Just as a reference, see the upper side band phase noise between the HMC-T2100 and the SMA100B below.

    I'm not saying your signal generators are the cause of this noise. I am suspect of clock coupling into the ADC analog inputs.

    HMC-T2100:

    SMA100B:

    Regards, Chase

  • Hi Hiroaki,

    I am familiar with the HMC-T2100 sig generator. This is not a good quality signal generator to use for a clock or analog input. It is too noisy. Please send us the FFT data as Chase requested above, and a block diagram with your exact test setup.

    It would also be advised, that high quality bandpass filters are used, not a homemade one, in-between the output of the sig gen to the input of the clock and analog input of the EVM.

    This is also suggested in the app note link I provided above.

    Regards,

    Rob

  • Hi,

    I attached the captured data. I'm sampling at 77MHz. The input signal is 327.25MHz CW(center of the Nyquist zone).

    The following is the clocking diagram.

    I understand the HMC-T2100 is noisy. It's understandable if the actual ENOB of the ADC is around 8,9, but it's not.

    It is actually around 5-bit. 

    In addition, the signal is pure at the coaxial connector and suddenly gets noisy at the 10Ω resistor just before ADC input(in the below schematic).

    The followings are the waveforms in the differential oscilloscope. The first is at the coaxial connector. The second is at the 10Ω resistor.

    They are captured in persistence display mode.

  • I'm sorry, but I forgot to attach the file.

    adc_data.csv

  • Hi Hiroaki,

    What are you using to capture the data?

    Would it be possible that you send us a FFT of the noise floor?

    Would it be possible to use a lower analog input signal?

    Do you see the same issues?

    Thanks,

    Rob

  • Hi,

    I'm using FPGA to capture the data.

    Does the FFT of the noise floor mean the data when a signal is not input?

    I can use a lower analog input signal.

    I think a full-scale input signal contributes to the best ENOB, but is it not true?

    This situation also happens in another ADC chip and on another board, so I think it is not because of the mounting failure.

  • Hi Hiroaki-san,

    Okay, just to clarify. You are using the TI EVM for the ADC34J23, but you are connecting the ADC EVM to a separate FPGA development kit?

    Not a TI data capture board/EVM?

    Couple more questions:

    Are you filtering the analog input from the signal generator to the input of the ADC EVM?

    Yes, noise floor means when you have no signal applied.

    Yes, to maximize dynamic range, its best to apply a fullscale input signal. But since you having issues, its best to back this off to see where the problem is. This is another reason, I am requesting a noise floor FFT.

    Regards,

    Rob

  • Hi,

    I am using the ADC34J23 and FPGA on the board I designed. Not a TI capture board/EVM.

    I am not filtering the analog input from the SG.

    I attached the data when I had no input signal.  It is 16K points of the ADC data.

    2728.adc_data.csv

  • Hi Hiroaki,

    Based on the data provided I have imported into our software, HSDC Pro and have generated the following noise floor. The ADC performance looks as shown in the datasheet for this device indicating no issue with the device itself. As Rob mentioned previously, the performance will not be as in the datasheet if using lower quality equipment without any filtering. Please try to use filter and a different signal generator.

    As you can see, the code variation in your data file is only 4 codes peak to peak. 

    Regards, Chase