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ADC128S102: Seeing the correct ADC output from the previous read - looks like data is coming out of the ADC the next conversion

Matty13763
Intellectual 440 points
Part Number: ADC128S102

Hi,

When I am trying to read Address 1 from the ADC, it takes me two 16 SCLK cycles before I see the correct data.

It appears like I need to read each address twice before the correct data appears. Is this accurate.

If I look at the timing diagram, it looks like on the same clock as ADDR0 is clocked into the A/D, the A/D sends out DB11. Is this possible? How does the A/D know what ADDR0 is before sending out DB11?

Am I missing something?

Thanks,

Jeff

  • 0
    TI__Mastermind 46200 points

    Hi Jeff,

    When /CS is pulled low, the ADC acquires the current channel selection, and on the forth clock starts the conversion process.  The channel address that is provided in this frame will be the channel sampled in the next conversion frame.  This is why the MSB DB11 bit is output at the same time as ADD0, the ADC is converting and shifting the data for the channel that was addressed in the previous frame.

    So yes, there is a 1 cycle delay between a channel address change and the conversion results for that new channel.

    Regards,
    Keith Nicholas
    Precision ADC Applications