Dear DAC support team,
We have been using DAC8802 for probing internal controller parameters (FPGA-based controller). After generating the correct clock and CS pulses for the SPI protocol, the rest of the pins: MSB and RS\bar, were given fixed values of 0 and 1, respectively, through FGPA gpios. The LDAC\bar pin was pulled down which should mean the output DAC register should automatically get the input register data. The SDI pin was transferring data corresponding to 2AAA bits with the address of channel A (01). Reference voltage Vref corresponds to 4V. However, at the output of the DAC stage, we are getting a -4V analogue value corresponding to all 14 bits high, in both the channels.
Kindly provide some suggestions as to what could cause both channels to see all 14 bits high. Note that when the ldac is pulled high the output corresponds to all the bits low(0), which follows the datasheet table - 2 on page 13.
Attaching a screenshot of the schematic.
Regards,
Vihan
