This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38J82: DAC SYNC not asserted after decrease lane rate

Part Number: DAC38J82
Other Parts Discussed in Thread: DAC38J84EVM, LMK04828

Hi there,

We have a working system with Xilinx Ultrascale FPGA JESD204 TX to DAC38J82. The FPGA JESD is configured at 8 Lanes with lane speed at 10Gbps. Reference clock to both the DAC and the FPGA JESD204 are both at 250Mhz for 250MSPS. Sysref at  7.8125Mhz.

Now to support a system with a lower symbol rate at 150MSPS or 175MSPS, we start re-configure the FPGA JESD204 and the DAC. The FPGA JESD with 8 lanes at 6Gbps and reference clock at 150Mhz. Sysref at 6.25Mhz. But now the SYNC signal does not get asserted. 

  • Hi, I have a few questions:

    Can you add more details about the operating mode for the DAC? Specifically, the sample rate and interpolation. I am confused how the DAC is operating in 82121 mode with a serdes of 10Gbps since it should not be that high. From what I can tell, the data rate has dropped to 60% the original frequency, however sysref has changed to 80% the original frequency. Is this desired? Having the extra details will help up answer better.

    Regards, Chase Wood

  • Hi Chase,

    It is 42111. The FPGA JESD TX has 8 lanes, but the data outputs to 4 lanes upon a control_sel for lane 0-4 or lane 5-7. So only 1 DAC channel has output.

    The current Interpolation is 8x. 

    10Gbps is the line rate on the Xilinx JESD TX configuration, which yields 250Mhz JESD TX core clock that gives a max 250Msymbol/s rate for our system. With 8psk and 9/10 FEC, the actual throughput to the DAC is ~660Mbps. on the DAC side, it is configured at full rate with 5xMPY.

    Now we need to reduce the symbol rate to 150 or 175 , so the lane rate of the JESD TX is changed to 6Gbps or 6.8 Gbps. We started testing with the 150Msymbol/s, i.e. JESD TX core clock at 150Mhz. 

    With the current 250Msymbol/s working system, both DAC and FPGA JESD TX has the same RefClk at 250Mhz and Sysref at 7.8125Mhz. Now we tried the following refclk and sysref configurations but no luck.

    1) DAC refclk at 250Mhz, FPGA JESDTX refclk at 150Mhz, Sysref at 6.25Mhz

    2) DAC refclk at 150Mhz, FPGA JESD Tx refclk at 150Mhz, Sysref at 6.25Mhz


  • Hi Chase,

    One more thing to add on.

    After only re-configure the FPGA JESD TX to 6Gbps line rate (150Mhz core/reference clock). And doesn't change anything else, i.e. keep the actual differential clock input to the DAC and FPGA JESD TX at 250Mhz, sysref  at 7.8125Mhz and the same DAC setting. It still works with verified waveform captured on UXA center F at 1.2Ghz, 8psk constellation, 250MSymbol/s

  • Thanks for the added details. I will match your configuration on our EVM hardware early next week and will let you know what I find out.

    Regards, Chase

  • Hello,

    I've brought up our EVM in LMFS=4221 mode and for 8x interpolation with data rate of 250MHz, the serdes rate comes out as 2.5Gbps. I'm not sure where you are getting a 10Gbps line rate from. The device would have to be using just a single lane (LMFS=1241) to get 10Gbps at these settings. I've verified that the EVM works at both 250MHz and 150MHz data rate for 8x interpolation in the LMFS=4211 mode. What I truly I don't understand is how your setup is working (and how is SYNC is being asserted) if the FPGA is sending data at a different rate than the DAC is expecting to receive. Is the link stable like this? Can you explain where 10Gbps is from?

    Regards, Chase

  • Yes. the Serdes rate is 2.5Gbps with 250Mhz data rate. 

    The 10Gbps Line rate is the Xilinx FPGA JESD TX PHY configuration with L=8. But like I mentioned before, the data only mapped to 4 lanes. 

  • The FPGA configuration needs to match the DAC configuration so you'll have to re-configure the Xilinx IP for a lane rate of 2.5Gbps

  • This part is a little confusing since this is a legacy design. As I mentioned before the system is verified on UXA with the 10Gbps line rate FPGA JESD TX configuration. (8psk constellation and 250MS/s). Since it is output to 4 lanes, doesn't that yield 2.5Gbps lane rate??  Here is the FPGA JESD204 PHY snip

  • The 10Gbps (which you are referring to as line rate) is what we refer to as total throughput for the xcvr, which is the line rate multiplied by the number of active lanes (2.5Gbps * 4 lanes = 10Gbps total throughput). The line rate is referring to the rate of data on each individual lane.

  • Great! That's what I thought as well. So to accommodate the lower symbol rate of 150MS/s, we need to decrease the lane rate from 2.5Gbps to 1.5Gbps. But that makes the Serdes PLL Output frequency fall out of the range of 1.5625-3.125Ghz. So does mean we need to change the RATE from full rate to Half rate so the Serdes PLL Frequency will be 3Ghz? If you can share the DAC register configuration for the 1.5Gbps lane rate, that would be great!

    Thanks a lot!

  • I'm not 100% certain from memory what all changes between the higher and lower serdes rates, but I will try to get the register sequence to you tomorrow early morning. Stay tuned!

  • Hello,

    So I've gotten the DAC38J84EVM running again as a DAC38J82 at 2GSPS in 8x interpolation mode (yielding the data rate of 250MSPS and a serdes rate of 2500Mbps). From the 2GSPS configuration, to reduce the sample rate to 1.2GSPS (in the same 8x interpolation, yielding a data rate of 150MSPS and a serdes of 1500Mbps), there are only a few register changes, as follows:

    • config59 (0x3B) change the value from 0x1800 to 0x800. This changes the SerDes PLL output divider from a 4  to a 2.
    • config62 (0x3E) change the value from 0x148 to 0x168. This configures the SerDes receivers to operate at eighth rate (for 1500Mbps) rather than at quarter rate (2500Mbps) as per Table 2. Lane Rate Selection

    Then, I change the FPGA configuration to the lower serdes rate using HSDC Pro. In your case, regenerating the bitstream file with the line rate adjusted to 1500Mbps should accomplish this.

    I then perform a DAC JESD core reset and trigger SYSREF. The DAC JESD core reset is done by the following register write sequence to register config74 (0x4A).

    1. write(0x4A, 0x0F20) - disables "init_state" and places the JESD block in reset
    2. write(0x4A, 0x0F3E) - enables "init_state" and holds the JESD block in reset 
    3. write(0x4A, 0x0F3F) - enables "init_state" and releases JESD block from reset
    4. write(0x4A, 0x0F21) - disables "init_state" and holds the JESD block out of reset

    To trigger SYSREF on the EVM, we have SYSREF set to run in Pin Pulser mode for the LMK04828. This means any pulse to the SYNC pin causes a burst of 8 SYSREF pulses to both the DAC and the FPGA. To get around this, we simply toggle the polarity of the SYNC input, which if the input is held constant, then inverting the polarity twice makes it seem as though a hardware pulse has been applied and we send off 8 SYSREF pulses.

    In summary, I recommend to start with modifying the FPGA IP for 1.5Gbps serdes rate. Then load your existing 250MSPS configuration to the DAC, then perform the following additional register writes to change the SerDes PLL for 1/8 mode, have a pause, then reset the JESD core, have a pause, and then trigger sysref.

    • 0x3B, 0x0x800
    • 0x3E, 0x168
    • delay
    • 0x4A, 0xF20
    • 0x4A, 0xF3E
    • 0x4A, 0xF3F
    • 0x4A, 0xF21
    • delay
    • Trigger sysref

    Attached is the configuration I am using on the EVM, but I can't incorporate pauses with our GUI, so the additional writes I've had to do manually through buttons on the GUI. sequence_1p5Gbps.cfg

    (Edited this post to change the file name from sequence.cfg to sequence_1p5Gbps.cfg)

    Regards, Chase

  • Thanks Chase!

    I will give it a try and let you know.

  • Hi Chase, 

    the attached configuration file sequency.cfg, is it for the lane rate of 2.5Gbps?

  • This is the sequence with 1.5Gbps serdes. So the data rate is 150MSPS and the DAC clock is 1200MSPS.