Other Parts Discussed in Thread: DAC38J84EVM, LMK04828
We have a working system with Xilinx Ultrascale FPGA JESD204 TX to DAC38J82. The FPGA JESD is configured at 8 Lanes with lane speed at 10Gbps. Reference clock to both the DAC and the FPGA JESD204 are both at 250Mhz for 250MSPS. Sysref at 7.8125Mhz.
Now to support a system with a lower symbol rate at 150MSPS or 175MSPS, we start re-configure the FPGA JESD204 and the DAC. The FPGA JESD with 8 lanes at 6Gbps and reference clock at 150Mhz. Sysref at 6.25Mhz. But now the SYNC signal does not get asserted.