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ADS1174: Serial data output behaviour

Dave Lockwood
Prodigy 10 points
Part Number: ADS1174

If this device is configured to SPI TDM output format, and CH1-4 reads are commenced on a DRDY hi>lo transition but do not complete prior to the next DRDY hi>lo (due to a relatively slow fSCLK), will the ADC output data stream reset to start transmitting the new CH1-4 results once this second DRDY transition occurs ? 

  • 0
    TI__Mastermind 40890 points

    Hello Dave,

    First, welcome to the TI E2E community.

    The data will effectively be corrupted if not read before the next DRDY.  The internal output data registers will be updated, so you will lose any of the previous data that has not already been clocked out of the ADC.  For example, if you only clocked 72 bits before the next DRDY (Channels 1 through 3), you would lose the data for channel 4.  In theory, you could possible correctly retrieve the next 3 channels of conversion results if you continuously clocked data, but there could be a shift in the bits depending on the relative phase of SCLK to the DRDY signal, so the data will likely be corrupted at this point.

    We recommend operating SCLK at a ratio of f-SCLK/f-CLK of 1, 1/2, 1/4, etc.  If operating SCLK equal to CLK or 1/2*CLK, then you will always have enough time to clock all 4 channels out of the device regardless of the ADC MODE.

    If I understand your question, yes, the data stream will reset with the new conversion results.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 10 points

    Thanks for your reply, which answers my original question.

    Can you explain why the two clocks (fSCLK and fCLK) need to be set in these ratios (and what happens if they are not ?), and is there any requirement to control the relative phasing of these two clocks ?

  • 0 in reply to Dave Lockwood
    TI__Mastermind 40890 points

    Hello Dave,

    These clocks do not need to be set in these ratios for proper operation of the device, but you will get increased noise if they are not.  The difference in the clocks will create spurs in the noise spectrum if they are not kept in the suggested ratios.  Ideally, the two clocks are in phase with each other and generated from the same clock source.

    Regards,
    Keith